Tool for connecting modules,download free,quick demo

Topweaver v2.0 A GUI-based tool for connecting HDL modules, also called structural integration. You can use it in ASIC, FPGA or CPLD designs.

FEATURES Extract ports from cell modules automatically Full mixed Verilog, Verilog 2001 and VHDL supported Automatically language recognition Connect ports in graph interface Great visual aid while connecting Smart Link technology enable you to connect ports automatically Bus combination and inout construction Generate Verilog/VHDL connection module automatically Output detailed module summary in HTML format Output formatted file list DelayGen ... Homepage:

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Quick Demo:
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