The NiosII is relatively new ( as lifelines go ) so not for 2005, but for 2006, or 2007 - imagine a low end Cyclone, with NIOS in the corner ?
Why ? NIOS and Microblaze are fpga resource optimised, but that is not mutually exclusive to any process level.
Altera will have numbers already on what a simple hardcopy NIOS port does, and probably also a good idea on what a little effort can do, were they to make it a more tuned HW cell.
My guess is we will see this [HW FPGA.Cpu] first from Altera, as they do not have a PPC, and already have the flows.
Yes. Look at the ST STW22000 device, the Cell processor?, and the Triscend devices. They all focus on the approach that "some FPGA is a good idea". Most discussion here is ASIC _OR_ FPGA - but why not offer both ? - start to be intelligent about what resource moves to HW/ASIC, and what stays in the smaller/simpler FPGA corner of the die ?
The tools are probably good enough now, the flows are proven.
I think the new Xilinx Strip die/flip chip would make this relatively easy to do, engineering wise. The politics is another matter :)
-jg