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PHB FPGA question

OK, pointy-haired boss question.

Given a ZYNQ 7020, speed grade 1. A 3.3 volt i/o bank gets a clock from an LVDS input. We have a resync flop in an i/o cell, clocked by this, with a D input from somewhere. Output is the strongest/fastest

3.3 volt option.

About what would be the typical prop delay from the clock to the output pin?

Online search yields a lot of words and no numbers. Experts say useful things like "it depends." The tools apparently give a range of timings over worst-case supply voltage, process, and temperature that vary by about 4:1 with no typical.

Second question: has anyone ever pushed an FPGA core voltage up to get more speed? In one little test I did, on an Artix 7, a simple case changed chip prop delay by 1 ns, from about 8.5 to about 7.5 ns, with a 70 mV core supply increase. That delay was essentially all combinational.

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John Larkin      Highland Technology, Inc 

The best designs are necessarily accidental.
Reply to
jlarkin
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niptechnology.com:

what typical?

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Reply to
Lasse Langwadt Christensen

Am 27.12.20 um 21:50 schrieb snipped-for-privacy@highlandsniptechnology.com:

Maybe LVDS is not the way to go. The LV means they want it somewhat fast, but power still does matter. The game is different with LVPECL or CML.

Because it really depends.The clock could be routed in a thousand different ways on the chip. It is usually best to use one of the typically 4 global clock nets, but there may be local ones that are placed nicely to your outputs. And avoid tri-state buffers. They are sloooow, alone for the logic they contain.

I have not used Zyncs, but mostly Virtexes.

The canonic way to get short clock to out delays would be to use a global clock net without any logic in front of it and then write a constraints file with the specs you need. Leave the work to the router. Don't be too greedy in the first round, you can put on the thumb screws later. First make sure that what you spec is that what you want. Sometimes is is not intuitive to specify that.

You can see in the static timing verifier where the ps are lost and where work for improvements is futile.

Never tried that. But I have built pipelines 24 stages deep. Do less combinatorial stuff in one stage and start early/parallel enough.

I think, if that would be possible in a reliable way, Xilinx would spec it that way and would ask for more money.

Gerhard

Reply to
Gerhard Hoffmann

It's possible, but might void the warranty. This is no different from over-clocking CPUs. You get incremental performance gain, but could have premature death. In any way, it's not the manufacturer's problem if you exceed the spec.

Reply to
Ed Lee

The clock into the FPGA is from a differential PECL comparator, so using an LVDS input makes sense. The output will be 3.3v cmos.

Rumor has it that, in general, lvds i/o is about a ns faster than cmos.

That's the standard answer: it depends.

There are a zillion appnotes and class notes, none of which include the word "nanosecond."

The clock could be routed in a thousand

I want my output to transition immediately after the first clock edge. Or maybe before.

--

John Larkin      Highland Technology, Inc 

The best designs are necessarily accidental.
Reply to
jlarkin

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