Hello everybody, and Happy New Year 2018!
I am new to digital design, here are some basic questions:
In particular for algorithm acceleration (e.g. arithmetic, cryptography, etc.), does it make sense to think both FPGA and ASIC when writing HDL library code?
And, about pipelining combinational logic, what maximum gate-delay granularity would be good (for fmax) on FPGAs? I am guessing a 2-gate delay maximum granularity before introducing a register does not pay off.
And, would similar considerations and a 2-gate delay pipelining be best for ASICs, too?
(Essentially, I am trying to find guidelines to write reusable HDL, but at the moment I am not even sure that such a thing in fact makes sense.)
Thanks very much in advance for any insight,
Julio