I finally got a test case for my FPGA async one-shot idea, hacked into a build for something else.
I got 17 different one-shots, with various pin locations and speed/drive strength settings.
Most of the outputs look like this, with remarkably consistent timing, edges within a few hundred ps. This is typical:
This one has minimum pin speed and drive strength, and was driving another chip on the board:
So, it looks like it will be safe to do this. I need to reset some ECL counters when an async event happens, and don't want to spin up a 500 MHz clock to do it.
The Xilinx tools didn't approve of us doing this.