FPGA minimum operating frequencies

Aug 26, 2003 2 Replies
N

Hello,



I was wondering if there were any *lower* limits on the clock frequency that can be used to clock FPGAs (in particular the Xilinx Virtex II : XC2V3000). I know there are certain kinds of high speed logic families using precharge-discharge operation, where the leakage sets a lower limit on operating speed. Is there such a limit for these FPGAs, and if so, what is it (ballpark figures are fine).



Thanks,



Nitin


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A

All,

Good answers, and they are correct.

All static, no precharge tricks.

You can go to 1 milli-hertz if you like.

Aust> Hello,

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W

Hello, In which reports of time can I see the maximum frequency or haw can I to calculate it?. I am working with ISE 5.1i and for the synthesis I use xst. Thanks, Falcón.

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