FPGA minimum operating frequencies

Hello,

I was wondering if there were any *lower* limits on the clock
frequency that can be used to clock FPGAs (in particular the Xilinx
Virtex II : XC2V3000). I know there are certain kinds of high speed
logic families using precharge-discharge operation, where the leakage
sets a lower limit on operating speed. Is there such a limit for these
FPGAs, and if so, what is it (ballpark figures are fine).

Thanks,

Nitin