floorplanning

Comments following.

Berty's general comment corresponds to a key part of solving the critical path: isolate it. Several times where I had trouble meeting critical timing (generally due to the tool's inability to map and/or place things well), I would break out that portion of the design (figuratively, by removing other constraints, or literally, by creating a test design just containing the portion of interest), and play with location and timing constraints. The smaller design, or loosely constrained design, routes MUCH faster, and you can iterate. In the process, I found out the the Xilinx 4k series (XL, XLA?) had a VERY fast input to output path, if you just needed an inverter. However, you had to choose the correct IOB groupings--the pins not only had to be close, there couldn't be any unbonded IOs between them. I also found that left-to-right was different from right-to-left for adjacent CLBs.

These and other design tricks were learned over the years by experimenting; it's how you learn to get the most performance out of the parts (along with reading the App notes and data sheets, and following the relevant newsgroups, etc.) You tend to leave some significant performance on the table if you just press "Run" and hope for the best.

Jason

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jtw
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There is some old floorplanning info on my website at:

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Plus the following is an example of a larger floorplanning projects:

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In particular, if you look at the MFILT design, (click on the picture to get the "BIG Picture" of an extremely well packed design. The following

3 designs also show very dense designs that are all well beyond the ability of the standard P&R tools to handle on their own.

What is great about the MFILT design, is that you can see detailed schematics for a significant portion of the design, including the floorplanning RLOCS by reading the patent, 6148313 at either

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or

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Philip

Philip Freidin Fliptronics

Reply to
Philip Freidin

HDL's not too bad for laying things out like this, if you have regular structures, because you can express the relationships algorithmically, and then easily mix and match this structural code with higher level, less speed critical HDL code.

My 2c, Jeremy

Reply to
Jeremy Stringer
[...]

The following layout tools have correlated models of LUTs and wiring delays:

Amplify from Synplicity Precision from Mentor And has Gabor said, PlanAhead, which now belongs to Xilinx.

Howdy Paul,

Mapping is a different issue than having good visability into actual delays or floorplanning as the others have been discussing. Interesting, but different.

Sorry - how exactly are you going to input your design? Using FPGA editor? User/input-error would kill you, not to mention portability is basicly zero - so you get to do it all again when you move from a Spartan II to a Spartan IIE.

But to address your main point, the vendors typically DO provide a way to do what you describe: you can instantiate the LUTs or FF's individually with HDLs or schematic tools. Then you're in full control of how stuff is mapped. Of course, this greatly hampers portability as well because different chips have different primitives.

For designs of a few hundred to maybe a few thousand LUTs, I guess I could see being able to map logic to LUTs manually. For anything more than that, do you really want to spend hours upon hours for even the simpliest of designs doing what the tool could do in mere minutes with (usually) acceptable results?

You'll also be missing out on non-obvious optimizations that the tools could do for you.

In my mind, the main goal of HDL is to provide a standard method of inputting a design that is mostly vendor independant. A side benefit is that in some cases, it provides efficient ways to describe more complex functions. If the tools aren't mapping logic correctly or efficiently, they need to be improved, not thrown out.

The above three tools would probably fall into the really slick and commerical category.

Have fun,

Marc

Reply to
Marc Randolph

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