error in xst

Hi I'm making a design and my top uses 2 differents models of memory (ROM) that I declare in vhdl using an array structure. But I got an error at the end of the top's synthesis: " FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. " I don't know what it is due to but if i comment one of the component ROM (only the instantation not declaration) there is no error , it's only when there is the two memories block. I chek up for for name signal in each component, name are different.

Does someone know this problem ??

Thank You


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ok i found the error I have made an shift register with an array of std_logic_vector and I tried to access directly to a part of it cpt_V_reg(6)(8 downto 3), and i use this signal to adress the memory block with an intermediate signal for the adress and it seem to be not very good to do that.

But I found in xilinx website that this problem should have been fixed since the 6.1i release of foundation and I got the 6.2i so it's not so fix , but i don't know for 6.3i version Should I advice a Xilinx FAE?? And if yes who (i'm french student so...)?


component memoire_symbole is Port ( clk : in std_logic; adress_V : in std_logic_vector(5 downto 0); adress_H : in std_logic_vector(6 downto 0); symbole : out std_logic_vector(7 downto 0)); end component;

mem1 : memoire_symbole Port map( clk, adress_V(8 downto 3), "

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