Hi I'm making a design and my top uses 2 differents models of memory (ROM) that I declare in vhdl using an array structure. But I got an error at the end of the top's synthesis: " FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. " I don't know what it is due to but if i comment one of the component ROM (only the instantation not declaration) there is no error , it's only when there is the two memories block. I chek up for for name signal in each component, name are different.
Does someone know this problem ??