Enum type as array range

yes

No, it's a good idea.

I see. Maybe like this:

------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity alu_test is end alu_test;

------------------------------------------------------------------------------- architecture sim of alu_test is subtype ALUSLV is std_logic_vector(7 downto 0); type ALUTyp is (AD, ADC, SU, SUC, CM, CMC, AN, LOR, LXR, SR, SC, AER); type ALUstyles is array (ALUTyp'left to ALUTyp'right) of ALUSLV; constant init : ALUstyles := (AD => x"42", ADC => x"ff", others => x"00"); begin

-- sim processes end architecture sim;

-- Mike Treseler

Thanks. Shortly ago, I got word back from a friend who had borrowed my one book that actually talked about this. But your example shows me I was mixing my type def with my constant declaration.

I am unusually tired tonight and am packing it in. I see I am making more errors than I am fixing :) I will hate to see what errors the simulator gives me when I try to compile tomorrow.