Hi, there:
My active implementation of two modules are all correct, P&R are perfect. However, during assembly stage, a small number (4) of wires literally got unrouted and returned to green flywires after P&R is done. In the fpga_editor it is labeled as GLOBAL_LOGIC0, and it lies deep in the middle of the reconfigurable module's AREA_GROUP...On inspecting active implementation, this wire IS routed, and the individual modules are perfectly routed too...
What may I do with this?
Thanks. Cody