doubling clock rate does what to power consumption?

Question

Hi folks,Been checking the archives for an answer to this one without much luck...What does doubling the clock rate of a design on an FPGA do to the powerconsumption (in general - I am just looking for a rule of thumb here..)?If you need some assumptions to answer:Assume:    critical path is a 25-bit carry chain in an adder.    a highly pipelined design occupying most of the device.Not sure what else would be useful assumptions-wise - please feel free toadd your own!  :-)Also, if I double my clock rate and reduce my hardware by half due tosharing hardware over 2 clock cycles, obviously the reduced hardware willreduce power consumotion and the increased clock will increase powerconsumption, question is, which is the overriding factor? (the clock Iguess?).Again, just looking for a rule of thumb.Cheers,Ken

Nicholas C. Weaver · Accepted Answer

Back o the envelope..Dynamic Power = CV^2F.Static Power = Constant...Since you aren't scaling the voltage, if you double the frequency,what happens to the dynamic power?And given that the leaking (static) power isn't half- the powerdissipation yet.Static vs Dynamic.Also, logic which changes burns power, so such interleaving willprobably reduce bit-history effects, upping power.-- Nicholas C. Weaver

Austin Lesea · Answer

Ken,Easy,  just use the power estimator spreadsheet.AustinPS:  generally speaking, if the dynamic power is dominating, CV^2F=P impliesthat the power will double if F is doubled, but there are lots of otherfatcors you need to pay attention to, such as what the IOs are doing (did thedata rate double there as well?), etc.Ken wrote:

doubling clock rate does what to power consumption?

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