PCB VERIBEST 1998 - 2002 (2026 Update)

Hi,

I'm looking for an old VeriBest Design Capture release from 1999.

I found this old file list, which contains:

PWAADP01.ZIP 1,459,067 31/08/99 PWAADP02.ZIP ... PWAADP28.ZIP

ANALOG AND DESIGN CAPTURE V99.0A (C) VERIBEST [XX/28]

The files appear to be a 28-part split archive of VeriBest Analog and Design Capture V99.0A.

I'm particularly interested in finding the original PWAADP01–PWAADP28 ZIP files, or any archive/tape dump containing them.

Does anyone here still have these files, or know where this release originally came from (BBS, FTP site, CD, DAT/tape archive, etc.)?

I'm also interested in any information about the original file area where these were distributed, possibly under directories such as:

/CAD /CAD'S /EDA /PCB

The file list I have is dated September 3, 1999, so I'm trying to trace the original source or an archival copy.

If you have the files, an old BBS/tape dump, or even just information about where they might have been archived, I'd be very grateful.

Thanks!

I am crossposting as a person who reads a different newsgroup might give a better answer.

Awe74 wrote in comp.arch.fpga - |---------------------------------------------------------------------| |"Hi, | | | |I'm looking for an old VeriBest Design Capture release from 1999. | | | |I found this old file list, which contains: | | | |PWAADP01.ZIP 1,459,067 31/08/99 | |PWAADP02.ZIP | |.. | |PWAADP28.ZIP | | | |ANALOG AND DESIGN CAPTURE V99.0A (C) VERIBEST [XX/28] | | | |The files appear to be a 28-part split archive of VeriBest Analog and| |Design Capture V99.0A. | | | |I'm particularly interested in finding the original | |PWAADP01â??PWAADP28 ZIP files, or any archive/tape dump containing | |them. | | | |Does anyone here still have these files, or know where this release | |originally came from (BBS, FTP site, CD, DAT/tape archive, etc.)? | | | |I'm also interested in any information about the original file area | |where these were distributed, possibly under directories such as: | | | |/CAD | |/CAD'S | |/EDA | |/PCB | | | |The file list I have is dated September 3, 1999, so I'm trying to | |trace the original source or an archival copy. | | | |If you have the files, an old BBS/tape dump, or even just information| |about where they might have been archived, I'd be very grateful. | | | |Thanks!" | |---------------------------------------------------------------------|

I do not know them. Rick Filipkiewicz gave me the impression that Mentor bought VeriBest.

Veribest is referenced in other posts. E.g.

Message-ID: snipped-for-privacy@algor.co.uk>

Date: Thu, 20 Dec 2001 10:12:05 +0000 From: Rick Filipkiewicz snipped-for-privacy@algor.co.uk>

Newsgroups: comp.arch.fpga Subject: Re: Spartan-IIE schematic symbol?

|--------------------------------------------------------------------------| |"We have a very similar thing for VeriBest (now owned by Mentor) | |schems. In some | |form or another we have been auto-generating schems. from pinout files | |since we | |moved to CPLDs from PALs. | | | |For the original versions we did use a ``canned'' part placed on a | |primitive | |schem with wires connected to all the part pins and the wires had temp | |names | |related to the parts pin names. | |Then used a tool that came with the schem editor to rename the wires | |that were | |"live" and delete the rest. This auto-schem was hidden in a hierarchy | |block. | | | |We can now contruct the whole thing from the ground up using schem | |editor's list | |of symbols which includes, for a ViretxE part, 8 ``bank'' symbols, a power| |block, and a configuration block." | |--------------------------------------------------------------------------|

Message-ID: snipped-for-privacy@trw.com Date: Mon, 16 Jun 2003 08:00:10 +0000 From: Martin Thompson snipped-for-privacy@trw.com Newsgroups: comp.lang.vhdl Subject: Re: Veribest Setup

|----------------------------------------------------------------------------| |""Yu. B" snipped-for-privacy@enel.ucalgary.ca> writes: | | | |> Hi, all, | |> | |> I am new to VHDL. I installed the VeriBest VHDL software and loaded up the| |> dummy .vhd file as listed below: | | | |First thing... Veribest got bought by Mentor Graphics a long time | |ago. VB VHDL is now no longer being actively developed, but Mentor | |should be alright about transferring your licenses to ModelSim (at | |least they were in our case). | | | |> ---------------------------------------------------------------------- | |> ENTITY serial_adder IS | |> | |> END serial_adder; | |> | |> ---------------------------------------------------------------------- | |> | | | |I think that ought to be OK! Not a lot to go wrong... | | | |> | |> However, whenever I tried to compile the file, I got the error message | |> ---------------------------------------------------------------------- | |> VeriBest VHDL Compiler - 15.01.00.14 | |> | |> | |> | |> ------------------- | |> | |> 1: b14^D | |> | |> ^^^ | |> | |> [Failure] Syntax error : received IDENTIFIER | |> | |> while expecting COMMENT | |> | |> or 'architecture' or 'configuration' or 'entity' or 'library' | |> | |> or 'package' or 'use' | |> | |> | |> Done | |> | |> ---------------------------------------------------------------------- | |> | | | |Very bizarre - are you using the GUI or the command line? You could | |try using the opposite method and see if that changes things. | | | |Another thought - my newsreader shows a CTRL-D character after the | |b14, I wonder if that has got into your file somehow and confused the | |compiler... | | | |Sorry not to be more help :-( | | | |Martin | | | |-- | | snipped-for-privacy@trw.com | |TRW Conekt, Solihull, UK | |

" | |----------------------------------------------------------------------------|

Message-ID: <bq7p8t$o0e$ snipped-for-privacy@mira.e-technik.uni-dortmund.de>

Date: Fri, 28 Nov 2003 15:23:09 +0000 From: Edwin Naroska snipped-for-privacy@ds.e-technik.uni-dortmund.de>

Subject: comp.lang.vhdl FAQ part 3 of 4: products & services

|------------------------------------------------------------------------| |"VeriBest, Incorporated | |USA: | |6101 Lookout Road | |Boulder, Colorado 80301 | |Phone: 303.581.2300 | |Fax: 303.581.9972 | |toll free: 800.VERIBEST | |WWW:

| |Email: snipped-for-privacy@veribest.com | |United Kingdom: | |44.1793.511199 | |Germany: | |49.89.96284.0 | |France: | |33.1.41.76.35.00 | |Nordic: | |46.8.92.54.00 | |Asia/Pacific: | |852.2.893.3621 | |Japan: | |81.3.3797.5277 | | | |Company: | |VeriBest, Inc. is a broad line supplier of EDA solutions that enable | |companies to solve their critical business issues by doing more and | |spending less. VeriBest pioneered the Windows NT EDA market by | |introducing its VeriBest PCB design solution in 1994 and continues to | |offer the best EDA price/performance available in the industry. | | | |VHDL Products: | |VeriBest Graphical High-Level Design: VeriBest Graphical High-Level | |Design is a language independent, graphical, state-machine entry and | |debug environment. VBGHLD includes a state table editor, a state diagram| |editor and a state flow graph editor. VBGHLD is integrated with VeriBest| |Design Capture to give you a single environment for your design | |definition needs. VBGHLD outputs both VHDL and Verilog. | | | |VeriBest VHDL: | |Introduced at DAC '96, VeriBest VHDL is a VHDL 1076-93 compliant | |simulator offering unique debug features such as a Network Traverser. | |VBVHDL is an Windows NT-product and utilizes standard NT ease-of-use | |features such as signal drag-n-drop into the various display and debug | |features. | | | |VeriBest High-Level Design: | |VeriBest High-Level Design is a VHDL/Verilog synthesis application that | |outputs VHDL and Verilog for post-synthesis simulation and outputs | |data for the VeriBest Design Optimizer." | |------------------------------------------------------------------------|

Message-ID: snipped-for-privacy@4ax.com Date: Mon, 22 Mar 2010 23:27:03 +0000 From: Jonathan Bromley snipped-for-privacy@MYCOMPANY.com Subject: Re: Finally, selling my old Xilinx/Viewlogic software package

|---------------------------------------------------------------------| |"On Mon, 22 Mar 2010 20:38:42 +0000, Peter wrote: | | | |>Towards the end of my era of doing complicated logic designs, a very| |>nice product was from somebody like Altera. It was a FREE VHDL | |>compiler, crippled to work with just a few low end devices e.g. a | |>22V10. | | | |Cypress WARP, maybe? I designed a good few PAL/GAL | |devices with it. There was a cut-off-at-the-knees | |version of the Veribest VHDL simulator, too - | |can't remember who shipped that. I still have a | |copy on my machine, but I can't get it to run under XP. | |-- | |Jonathan Bromley" | |---------------------------------------------------------------------|

Message-ID: snipped-for-privacy@posting.google.com>

Date: Thu, 18 Sep 2003 16:56:52 +0000 From: Michael Dunbar snipped-for-privacy@ntlworld.com Newsgroups: comp.arch.fpga Subject: Re: Actel Desktop Schematic Viewer

|--------------------------------------------------| |"Andrew Paule snipped-for-privacy@qwest.net wrote in message| |news:<6E2ab.725$ snipped-for-privacy@news.uswest.net>... | |> What format are they in? | |> | | | |Veribest, *.sbk and *.blk files." | |--------------------------------------------------|

Message-ID: snipped-for-privacy@posting.google.com>

Date: Mon, 13 Jan 2003 07:08:23 +0000 From: john jakson snipped-for-privacy@yahoo.com Newsgroups: comp.arch.fpga Subject: Re: SChematic design approach compared to VHDL entry approach

|----------------------------------------------------------------| |"Surely didn't every schematic package have various HDL output? | | | |Last one I used Intergraph/Veribest/goneaway had Verilog, VHDL &| |couple of others [. . .] | |[. . .] | | | |[. . .]" | |----------------------------------------------------------------|

Archives are at

and Good luck! (S. fuer Kontaktdaten!)

If he really wants to buy it then a company which you named could sell it to him.

(S.

fuer Kontaktdaten!)