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Synchronous design and power consumption

Can anybody give me hard facts on the power consumption ramifications for the following two design styles:

a) Fully synchronous design with appropriate clock enable signals for "slower" clock domain areas of the design.

b) Asynchronous design generating slower gated clock signals for those slow clock domain areas of the design.

In a), each flip-flop has to load the clock input capacitors on each clock transition, even if the clock enable signal is false and that will consume energy. But how much?

In b), we are sure to conserve energy, but at the cost of a dramatic increase in design complexity, because we have to use signal synchronisation contraptions whenever we go from one clock domain to another clock domain.

Is the added complexity of approach b) really worth the power savings I get out of it?

:)

Klaus Schleisiek

kschleisiek AT XYfreenet.de If you want to send me an e-mail, use above address and remove XY

Reply to
Klaus Schleisiek
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Klaus -

I can't give you hard numbers, but in an FPGA I think the power savings of b) vs. a) would be extremely small, possibly not even measurable. In a custom ASIC, where the clock trees themselves can consume a lot of power, it may be worth the effort. In an FPGA, where clock routing is a dedicated resource, that is not a factor. Also, flip-flops generate switching currents when their output state changes, not when their clock input toggles. I wouldn't even try to quantify the power difference between a) and b). For several reasons, go with a) and don't look back!

Rob

Reply to
RobJ

I think your best bet then is to get an FPGA eval board and run some experiments. Not with your real design. Just build a design with a bunch of counters running at different rates. Then try a) vs. b) and measure the actual core current consumption. You've got me curious now. If you do it please post your results.

Rob

Reply to
RobJ

I'm talking battery operated missions here. Yes, I am interested in 10 mWatts savings.

Klaus Schleisiek schrieb:

Reply to
Klaus Schleisiek

Hi,

I don't have hard nos. either but definately clock running all the time is going to consume maximum power. As far as clock gating is concerned, its is definately worth the effort if you want to have battery operation with FPGAs, but that means that you won't be able to use clock routing resources since you will be generating gated clock. Be extremely careful in this case - I would recommed running formal verification tool and also run gate level simulations with SDF.

If you don't mind waiting, I believe Stratix II or Virtex IV is going to have true gated clock support. If you use clock enable, you are only saving flop switching power.

-Purvesh

Reply to
Purvesh

After poking around a little I've come to these conclusions:

  1. I don't know enough about the details of FPGA power consumption to even comment on it.
  2. FPGAs are not a good choice for very-low-power battery-operated applications.

Bowing out of this thread.

Rob

Reply to
RobJ

FPGA's usually have some external dedicated clock inputs. What about gating those (externally) with a gate? Then it's true gating.

Jeroen

Reply to
Jeroen

You might also want to do some "what-if" analysis using XPower.

Brendan

Reply to
Brendan Cullen

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