Design Rule Check

Nope! It's vague. PCB layout design rule check, or circuit connectivity/electrical rules check, or device sizing/spacing violations in a chip layout? ...Jim Thompson

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Thinking outside the box... producing elegant solutions.

You mean, like a body check in hockey?

I see no file, or link... then I'm often in the dark.

George H.

You name it, we have to live with it.

No, I mean, like, WRONG!

You are no doubt too young to remember hand-drawn schematics and taped mylar layouts. It took two people two days to check a decent design, one calling out the connections and the other tracing a blueline of the tapeup.

Now, click, it's done in a few seconds.

I used those & Win's older than I am. On 2nd thoughts we used acetate & crepe paper tape, not mylar. I cursed the software that replaced the tape method.

NT

Both circuit connectivity/electrical rules check, and device sizing/spacing violations are built into _my_ PSpice. (I cheat just a wee bit... having written scripts for the device templates such that they auto-report violations. Circuit connectivity/electrical rules check comes with PSpice Schematics.) ...Jim Thompson

I have excellent results with my DRCs. I set up the PCB rules and it does what I tell it to (or doesn't do what I forget to tell it to do).

I larely ignore schematic ERC as no one does digital schematics.

Tim

-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website:

As one progresses further and further in a constrained space, making changes and improvements, the design rule safety margins began to tighten, or maybe to disappear. Wide traces, ground planes, holes sizes and clearances are degraded. Ad-hock rule rationalizations spring up.

Can I buy a verb?

What ever you are smoking, I'd like to try. Or is it jimsonweed?

Why would you do that? It's a simple check and it will find a lot of stupid mistakes.

When I worked for LM, the board my FPGAs was supposed to go on was a mess. I asked if any DRC/ERC had been done. The answer was similar to yours ("that's too much work"). It would have shown them how sorry the schematic was.

We used D-size sheets of mylar, pin aligned on a light table. Padmaster, one sheet for each of the trace layers, and a rubylith power plane sometimes. We sent it out to be photographed to film, which we sent to the PCB house and got back.

We use black tape on a mylar sheet for each layer, but some people used red/blue transparent tape on the same sheet, for two PCB layers. I thought that didn't work very well.

I loved PCB CAD from day one. I got tired of leaning over a light table, holding my breath, trying to get two traces between the pins of a DIP.

I'm laying out a board now. It took under a day to enter the schematic, and might take a day, maybe two, to do the layout.

We do full schematics of all boards, digital or not. FPGA guts are all text, although some of the tools are graphical/block diagrams at the top level, which is sort of a schematic.

We check PCB schematics for stuff like single-ended nets. And we read the netlist to make sure some spelling error didn't create two nets where we want one.

We pretty much use PADS as intended. A couple of gotchas:

Sometimes we set clearances to, say, 8 mils, run the check, and one or two tiny parts fail the clearance checks. We look at them and go.

Some parts, like connectors, sort of fall off the edge of the board, and PADS throws an error. We ignore it.

Of course, having something with a brain go over a layout is helpful with stuff like cross-talk.

I can still remember getting a board layout from collaborators and looking (with my boss) at the tracking around a 733 amplifier that wrapped an input around an output. We were both got the horrified.

We fixed that before we had our versions of the board made, and they worked fine.

We did warn our collaborators, but they still had 200 copies of the board made and loaded, and could only make the board work by pulling out the 733 and cobbling in a two transistor discrete amplifier.

If you had understood my statement, you'd have realized I don't create large digital schematics... nor does anyone else (by projection).

Since I do largely analog designs, ERC is superfluous, and digital sections are easily verified.

Some analog designs may require abusing ERC anyway, e.g., gates paralleled for extra drive.

(FYI, I /do/ use ERC assignments on digital pins, and the check is automatic. I never need to correct ERC errors, because I always wire them right the first time.)

Tim

The crepe tape was for single-sided. For 2 layer you could use blue and red mylar tape with black crepey donuts and they would do a color separation photographically.

Don't miss that one bit.

--sp

Sometimes you have to throw 'net ties' around to (sort of) create two nets where there is really only one. Eg. Kelvin connections.

I don't think the DRC on schematics is all that useful, but it can find a few things in complex hierachical schematics, if they don't get lost in all the bogus warnings about no driving source etc.

--sp