Debugging error in VHDL

Feb 23, 2005 0 Replies

I have got two errors in my VHDL program of an ALU. The errors ar



HDLParsers:3324 - IN mode Formal enable of add8bit_wc wit



no default value must be associated with an actual value HDLParsers:162 - Read symbol PORT, expecting ';'



Anyone there please help me out


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