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DC fifo behaviour at underflow/overflow

y

I disabled built-in protections and forcefully overwrote protections in user logic.

rdreq Thanks

C_VECTOR (31 DOWNTO 0);

;
;
;
;

OGIC_VECTOR (31 DOWNTO 0);

WNTO 0);

URAL;

G;

STRING;

ATURAL;

ATURAL;

;

STRING;

;
;
;
;

OGIC_VECTOR (31 DOWNTO 0);

;

C_VECTOR (31 DOWNTO 0)

There is a known bug in Quartus 11.1 that applies to use_eab => "ON". According to the knowledge base, it was fixed in 11.1SP1.

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There is another known bug that is not fixed in 11.1SP1/11.1SP2, but it only applies to use_eab => "OFF" so you shouldn't care about it.

Looking at your parameters, rdsync_delaypipe => 5 and wrsync_delaypipe => 5 sound like an overkill. It's unlikely that value of 5 really improve anything over value of 4. And if overflow happens nevertheless (don't ask me how, I don't know) then longer sync pipelines certainly make self-recovery more difficult.

Reply to
Michael S
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No, I did a functional simulation in Quartus 9.1 internal simulator. Quartus 9.1 ISIM can't simulate Stratix-IV, so I told him that it is Cyclone-III. For a functional simulation it should make no difference.

Reply to
Michael S

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