High to Low voltage shifter

I am designing a CMOS Schematic in which there are both 3.3 V and 1.2 V power(0.13 um process). So when the data or clock is transferred from the 3.3V circuit to the 1.2 V circuit, I need to scale down the maximum Voltage of the data from 3.3 V to 1.2 V.

Since 1.2V is not too low, I decided to use a buffer/inverter circuit with 1.2 V power supply (VCC or VDD). With a CMOS data (3.3 V /0 V) as the input of this buffer, the output is scaled down to 1.2V (/0V). Apart from a small duty cycle error, the circuit seems to be working. But I=92ve seen other circuits which does the same (instead of an inverter switch, a nmos switch is used) but no paper/book explains properly why other circuits are preferred over a simple inverter.

My question is, if anyone has worked on mixed power supply circuits before and is there any potential problem here than I am overlooking?

Reply to
jake.cubert
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Assume the 3.3V signal at point [A] : connect a resistor between [A] and [B], connect two diodes in series between [B] and [GND], then at point [B] the signal will be 1.2 V

Reply to
Jean-Christophe

Hi Jake

When you say 'nmos switch' do you mean an N channel FET? If so, this will allow you to interface to a HIGHER voltage (limited by the drain source rating of the FET), so 3v3 logic can interface to, say 12V, 24V etc).

However, this only allows data to flow one way. If you have an input AND output line that needs level shifting, most people these days use bidirectional level translators (guaranteed rise time, data rate etc)

-- Bill Naylor

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Since 1.2V is not too low, I decided to use a buffer/inverter circuit with 1.2 V power supply (VCC or VDD). With a CMOS data (3.3 V /0 V) as the input of this buffer, the output is scaled down to 1.2V (/0V). Apart from a small duty cycle error, the circuit seems to be working. But I?ve seen other circuits which does the same (instead of an inverter switch, a nmos switch is used) but no paper/book explains properly why other circuits are preferred over a simple inverter.

My question is, if anyone has worked on mixed power supply circuits before and is there any potential problem here than I am overlooking?

Reply to
Electronworks.co.uk

When i said Nmos(N Channel FET) switch, I meant a 2 Nmos connected in cascode structure with the top NMOS drain connected to Power and the bottom NMOS source connected to ground. The structure is similar to an inverter structure, if you add an NMOS instead on a PMOS. The input,however, is complimented such that one NMOS gets a normal phase input and the other, inverted input.

I have the structure in this image,

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If you can see that schematic, LVCC is 3.3 V and DVDD is 1.2 V. So the input is 3.3 V TTL while the output is 1.2V TTL.

I also have another schematic on the right in that image, A simple 2 inverters connected in series. The 1st inverter is powered by 3.3 V, the second by 1.2V.

Reply to
jake.cubert

Since 1.2V is not too low, I decided to use a buffer/inverter circuit with 1.2 V power supply (VCC or VDD). With a CMOS data (3.3 V /0 V) as the input of this buffer, the output is scaled down to 1.2V (/0V). Apart from a small duty cycle error, the circuit seems to be working. But I?ve seen other circuits which does the same (instead of an inverter switch, a nmos switch is used) but no paper/book explains properly why other circuits are preferred over a simple inverter.

My question is, if anyone has worked on mixed power supply circuits before and is there any potential problem here than I am overlooking? :==========================================================================

Which chip are you using and what frequency is the clock. Does the datasheet say it can run at 1.2V and accept a 3.3V input signal?

If so you should be OK.

The Nmos trick is either for higher freq or cheap.

Reply to
mook Johnson

Since your inverter has 3.3V on its input you must be using transistors that can tolerate that voltage reliably, which typically requires thicker gate oxides and higher threshold voltages. The largest Vgs you can put on the inverter PMOS is -1.2V, when the drain is at 1.2V and the gate is at ground. With just 1.2V for Vgs the PMOS will not have a very high drain current and so the output rise time will be slow. At

1.2V you may get away with doing this, and you could make the PMOS larger to compensate for the small Vgs. I once needed to shift 3.3V signals down to 0.5V in a 0.35um process and the NMOS cascode arrangement worked very well. That's the advantage of the NMOS cascode circuit...it is fast and small even for very small output voltages.

Joe

Reply to
KJH

I'm puzzled. What NMOS cascode arrangement do you have in mind?

...Jim Thompson

--
| James E.Thompson, P.E.                           |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
 I love to cook with wine     Sometimes I even put it in the food
Reply to
Jim Thompson

I'm even more puzzled when persons make statements and then run from them. BS at its worst ?:-)

...Jim Thompson

--
| James E.Thompson, P.E.                           |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
 I love to cook with wine     Sometimes I even put it in the food
Reply to
Jim Thompson

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