High to Low voltage shifter

Assume the 3.3V signal at point [A] : connect a resistor between [A] and [B], connect two diodes in series between [B] and [GND], then at point [B] the signal will be 1.2 V

Hi Jake

When you say 'nmos switch' do you mean an N channel FET? If so, this will allow you to interface to a HIGHER voltage (limited by the drain source rating of the FET), so 3v3 logic can interface to, say 12V, 24V etc).

However, this only allows data to flow one way. If you have an input AND output line that needs level shifting, most people these days use bidirectional level translators (guaranteed rise time, data rate etc)

-- Bill Naylor

Since 1.2V is not too low, I decided to use a buffer/inverter circuit with 1.2 V power supply (VCC or VDD). With a CMOS data (3.3 V /0 V) as the input of this buffer, the output is scaled down to 1.2V (/0V). Apart from a small duty cycle error, the circuit seems to be working. But I?ve seen other circuits which does the same (instead of an inverter switch, a nmos switch is used) but no paper/book explains properly why other circuits are preferred over a simple inverter.

My question is, if anyone has worked on mixed power supply circuits before and is there any potential problem here than I am overlooking?

When i said Nmos(N Channel FET) switch, I meant a 2 Nmos connected in cascode structure with the top NMOS drain connected to Power and the bottom NMOS source connected to ground. The structure is similar to an inverter structure, if you add an NMOS instead on a PMOS. The input,however, is complimented such that one NMOS gets a normal phase input and the other, inverted input.

I have the structure in this image,

If you can see that schematic, LVCC is 3.3 V and DVDD is 1.2 V. So the input is 3.3 V TTL while the output is 1.2V TTL.

I also have another schematic on the right in that image, A simple 2 inverters connected in series. The 1st inverter is powered by 3.3 V, the second by 1.2V.

Since 1.2V is not too low, I decided to use a buffer/inverter circuit with 1.2 V power supply (VCC or VDD). With a CMOS data (3.3 V /0 V) as the input of this buffer, the output is scaled down to 1.2V (/0V). Apart from a small duty cycle error, the circuit seems to be working. But I?ve seen other circuits which does the same (instead of an inverter switch, a nmos switch is used) but no paper/book explains properly why other circuits are preferred over a simple inverter.

My question is, if anyone has worked on mixed power supply circuits before and is there any potential problem here than I am overlooking? :==========================================================================

Which chip are you using and what frequency is the clock. Does the datasheet say it can run at 1.2V and accept a 3.3V input signal?

If so you should be OK.

The Nmos trick is either for higher freq or cheap.

Since your inverter has 3.3V on its input you must be using transistors that can tolerate that voltage reliably, which typically requires thicker gate oxides and higher threshold voltages. The largest Vgs you can put on the inverter PMOS is -1.2V, when the drain is at 1.2V and the gate is at ground. With just 1.2V for Vgs the PMOS will not have a very high drain current and so the output rise time will be slow. At

Joe

I'm puzzled. What NMOS cascode arrangement do you have in mind?

...Jim Thompson

I'm even more puzzled when persons make statements and then run from them. BS at its worst ?:-)

...Jim Thompson