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clock split approach for 270MHz design in Spartan2E

I am trying to implement a different flavor of XAPP224 in order to have a 270Mbps serial to parallel converter (DVB-ASI application) in a XC2S200E-6 device. I thought to divide the VCO's 270MHz by two, to produce two 135MHz clocks and use a carry chain delay arrangement to shift one clock's phase. Then building a double serial-to-parallel and registering both outputs together I may end with the expected 10 bits. In this frequency I know it is hard to implement but if feasible I would appreciate your considerations and recomendations. The XAPP250 uses this delay approach but talks only about V2 and V2Pro end devices. Also, the XAPP250 says there is a ZIP file with VHDL source but the file I've found has Verilog files only. It could be translated to VHDL but to make things worst that application uses Symplicity (with synthesis attributes not available in XST) and I cannot afford to have a Symplicity tool to work with. I understand I shall need to design the whole circuit using absolute positioning of fabric resources. But, of course, better to start if I know I can make it working on this device. Of course there is no possibility to change device (to Spartan-3 or V2) at this moment. So, is there a hope for my case?

Thanks for your attention.

Reply to
AugustoEinsfeldt
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Augusto, I assume you know that every Virtex-4 drvice offers exactly that function, at up to 3 times higher speed, and on every pin independently. So, if you are flexible, it's all done for you... Peter Alfke, Xilinx Applications

Reply to
Peter Alfke

Or if the V4 is too expensive for Augusto's application, he could also check out the Spartan 3. For some parts and applications, S3's are even cheaper than Spartan II's, with more, better, and especially important for his application, faster resources.

Spartan IIE is like the Virtex-E... and I'd be a little shy of pushing the Virtex-E to 270 MHz. I seem to recall Ray doing some impressive stuff with Virtex-E's... maybe he can chime in. After all, there won't be too much logic running at that rate (some muxes and some flops... that's all, right?).

Good luck,

Marc

Reply to
Marc Randolph

Thanks for the replys. This application is cost sensitive and SP3 is the best choice for production but when the this design was made the SP3 was not easily available and customer is reluctant to use BGA packages (also because PCB costs). This statement in XAPP250's summary: "..With minor modifications, Clock and Data Recovery (CDR) is possible with Virtex-E and Spartan=99-IIE devices..." and since XC2S200E-6 is under this limits (I know it is barely bellow maximum) made me believe I could do it with this device I had in hands. If you believe I cannot do it I wont waste time trying and will ask customer to make a new PCB using SP3.

Reply to
AugustoEinsfeldt

As long as you are just doing the serial to parallel conversion at 270 Mhz, you should be OK. I'm pretty sure if you keep to one level of logic between flip-flops and hand place the flip-flops and LUTs you can get to 270 MHz in a virtexE-6. If doing PAR, you find out that you can't, you can use a 135 MHz clock, and by hand routing the segment from the pin to your first registers, you can clock the odd and even samples into separate shift registers, one clocked on the rising edge, one on the falling edge (or you can use the DLL to get you a 180 degree clock). You'll need to be clever with your bit counter: a binary counter is going to be too slow. Instead use a counter based on a shift register (such as a Johnson counter), but DO NOT use the SRL16 in this application because the minimum clock pulse width won't be met with a

270 MHz clock.

If your customer is going to be producing this in any volume and has not bought his parts, moving to SpartanIII may save more than the cost of respinning the board, and will greatly reduce your design effort.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
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Reply to
Ray Andraka

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