Convert some table into combinatorial circuit + optimization

Hi. Let's say, I have big table which is usually suitable to fit it in some ROM. But it's possible to construct some circuit containing only primitive gates that acts just as that ROM. Here is an example of converting tables from DES cipher into gates:

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I'm interesting, is there any automated way to do so, thus to have on output circuit with the smallest possible primitive gates (AND, OR, NOT, XOR).

Reply to
sdf
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Sure... you just write down the logic equations for each bit of the (data) output as a function of the (address) input and then run it through your favorite logic minimization routines that uses, e.g., Quine-McClusky or some other reduction technique. (The old program ESPRESSO automates all this... Google "logic minimization software" and you'll get plenty of good hits).

Unless you're talking very small ROMs, you'll usually find the implementation ends up being cheaper as a ROM. Years ago I manually programmed (using a bunch of DIP switches!) 32x8 PROMs to do hexadecimal to 7-segment LED converters -- PROMs were cheaper and more readily available than the somewhat obscure ICs that did the same thing. (You'd have thought the guys who designed the 7447/7448 would have fully decoded 0-F rather than just 0-9, but nooooo...)

---Joel

Reply to
Joel Koltner

If I have this right... You want the equivalent function of a rom but done with gates. Perhaps call it a data synthesizer.

Example: Address 0 9 address 1 17 address 3 22 address 4 9 address 5 11 address 6 255

I don't have any suggestions for using only logic gates. But this came to mind... If you have no repeated values, you might try an MLS generator (shift register + gates). Repeated data will need more logic. Possible, but a pita to figure it out. See

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IMO, a very interesting area in electronics..

D from BC British Columbia Canada.

Reply to
D from BC

Make the address decoder with the corresponding output for every position of the table and then minimize the logic. Depending on the linear complexity of the table, that can take very different amount of gates. BTW, the DES tables are specifically designed to be very nonlinear and irregular, so it would be tough to represent them as the logical function.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

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Reply to
Vladimir Vassilevsky

I had a co-worker who spent several days trying to make a more efficient implementation of an 8B/10B encoder/decoder using gates rather than ROMs... without success; I wasn't surprised. (I am aware that the original patent for

8B/10B shows a gate-level implementation, but it was written so long ago that I don't think ROMs were much of an option at the time.)
Reply to
Joel Koltner

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