Hi, I have a PCB design with a FPGA and other devices that require a clock input. Is it a good idea to first feed a single clock into the FPGA and then through the FPGA distribute this clock to the other devices?
Ben
a) Do the other devices need their clocks before the FPGA is finished Config ? b) Is added jitter on the clock a significant concern ? c) Do you have power save modes, where the FPGA is deprecated ?
If not, then is _is_ nice and flexible to route the clocks thru the FPGA, as ytou can do what you like with them later....
-jg
This depends on whether or not you can live with anywhere from no less than 30ps to possibly over 200ps of *extra* jitter and many more picoseconds if you are concerned about skew between replicated clocks.
If the other devices can live with ~300ps clock jitter, it should work with all current FPGAs with minimal (if any) hassle. If you need something better than that, you can find some VCO ICs capable of generating low-skew clocks with down to sub-picosecond jitter, so finding ones with less than 100ps jitter+skew should be easy and inexpensive.
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