Microsemi FPGAs

They use Synplify and Modelsim in a Microsemi Edition for synthesis and sim ulation. The tools are called from Libero SoC, their own 'wrapper' design f low tool. During the development of our product, the release of Libero SoC went from 11.0 to 11.7. Now 11.8 is out, and they are improving from versio n to version. For FPGA work both Linux and Windows is supported. For MCU wo rk, they are relying on eclipse, but some parts of the programming and debu g features from eclipse used to be windows only. For any JTAG programming f rom Linux, you have to get the FlashPro5 programming dongle. FlashPro4 was not supported for neither FPGA nor MCU programming last time I looked into it a year ago.

Design entry is typically done in a block diagram editing tool on toplevel. I could fairly easily integrate my external VHDL code without much hassle and that was an advantage as we were moving from Altera to Microsemi and go t rid of the schematic capture done in Max+Plus.

The implementation of the FPGA fabric is a matter of clicking buttons in th e GUI, but most of the process can be automated with Tcl. In 11.7 there was still one process step which was GUI only. I nagged them about this for so me years to get all process steps done by Tcl, but my volume was not large enough for them to listen.

We split the FPGA development and the MCU software on two engineers. Their version of eclipse called SoftConsole used to be a bit to tightly connected to the data provided by Libero SoC regarding allocating areas in the inter nal flash, but the separation into an export of a BSP from FPGA is improvin g. The SW guy needed to fire up the FPGA tool from time to time to fix some snags that happened because we shared the design on SVN.

Documentation for SW design when using IP modules from Microsemi is done wi th doxygen so it was pretty easy to start writing bare-metal code in the MC U for the various IPs that we used. When the FPGA platform was correct rega rding memory areas, the SW guy could do his dayily work direct in SoftConso le (on windows) with programming of the MCU code, downloading and debugging . FPGA fabric can be programmed separately from MCU area.

I found Libero SoC a bit less tedious than Vivado, but I had a learning cur ve.

I would agree, and due to the true flash storage of the configuration, ther e is no issues regarding how to store your bitfile on the board for a produ ct. Just get the JTAG connections right and each programming is persistent. Instant on. I would use the device again on anything which the M3 can hand le. Can run uC Linux, but we opted for bare-metal as we wanted to use only the internal 256k flash area. I was hoping for a Cortex-A or Cortex-R CPU, but they didn't have that on the roadmap.

If you stick to devices which are covered by the silver version of the lice nse, you only need to register once a year for the free (as in beer) versio n of Libero SoC.

We have done a couple of projects with them, and the tools haven't been bad to work with.

You start with a top level block diagram in which you place a block for the processor. There is a 'System Builder' tool that builds and configures the processor block and support logic around it (like adding in additional peripherals that are provided that aren't hard logic in the processor), which becomes a piece of your design, and then you add other blocks to represent other parts of your design (built with HDL, provided cores, or other block diagrams)). You can also just put down the symbol for the core MPU and build the stuff around it yourself if you need something a bit non-standard.

The one thing that is a bit frustrating is that block diagrams are 'auto-routed' and 'auto-placed' (auto-placing mostly on command), and the algorithms sometimes seem a bit strange. I find I tend to need to lock the major blocks so they don't go to strange places, and occasionally wish there was a similar option for the line.

The software side is Eclipse/GCC based and seems to run fairly cleanly. The only real issue I have seen is that the FPGA tools generate the Board Support Package files in a sub-directory of the FPGA design, and you need to copy those over to your Software Project directory as you hand them off between the team members.

They use Modelsim for the simulator and Synplify for synthesis. That's as good as it gets. Rest of the tools seem to be fine. I did a design with one of these parts last year - didn't come across anything particularly troublesome.

I didn't use the high level (Matlab/Simulink) based design tools so don't know how they compare to the Altera/Xilinx equivalents - I wouldn't expect them to be as capable as the latter.

They are. Lattice also offer good value on small/medium FPGA's (not SOC's) - I tend to use Lattice in preference to Altera/Xilinx.