An implementation of a clean reset signal

Eli Bendersky · 2006-10-05T07:43:51+00:00

Hello all,Following some discussion in these groups and reading a couple ofarticles (especially the first one turning up when you google for"asynchronous synchronous reset design techniques", it seems that thebest and the safest way to use resets in FPGA designs is to use aspecial synchronizer circuit that assures that the reset of the FFs isasserted asynchronously, but is deasserted synchronously.The circuit is something like (kindly borrowed from the aforementionedarticle):~~~~~~~~entity reset_synchronizer isport( clk, async_reset_n: in std_logic; sync_reset_n: out std_logic;);end reset_synchronizer;architecture rtl of reset_synchronizer is signal rff1: std_logic;beginprocess (clk, async_reset_n)begin if async_reset_n = '0' then rff1

Oct 05, 2006 47 Replies

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Bob Perlman 19 years ago

Uh, I did. Took me 20 minutes to type it up, too. I'm not exactly sure what the disagreement is: if you have FFs controlling TriState enables, you should initialize them asynchronously. Whether that's done by an end-of-config reset or some other reset signal doesn't really matter--you need the asynchronous reset.

And I didn't even get to the open-the-bomb-bay-doors and throw-the-countermeasures-out-the-back-of-the-plane and start-radiating-the-patient signals. Proper design etiquette demands that they be initialized immediately, too. (Yes, those signals go through other interlocks, but as soon as you rely on redundancy, it ceases to exist.)

Bob Perlman Cambrian Design Works

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Jim Granville 19 years ago

Correct, and you also need Async control, in such paths as Watchdog. If the wdog fires due to clock failure, and your reset is only Sync, guess what happens next ? Maybe the FPGA core does not care, but the system design certainly does, and if the FPGA cannot handle this, then downstream, logic must be added.

-jg

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Ray Andraka 19 years ago

Yup, that's what I do for those cases that need an async reset. The PGM pin on the FPGA works fine as a reset, as it instantly drives all but a few pins to hi-Z. FPGAs are not really designed for Async reset; the tools do not support it very well (timing analysis issues). If it were up to me, I'd remove the async resets from the internal logic and reap the increased performance that would result.

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Ray Andraka 19 years ago

Doesn't have to be. There are flip-flops in the IOBs for the tristate control, but they can be bypassed.

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Eli Bendersky 19 years ago

This isn't different from the "normal" async reset, however, where the reset signal isn'f filtered. The solution usually used is an external reset circuit (they come packed in nice tiny ICs these days) that provides a clean reset signal of 200 ms (or whatever you set it to) whenever there's a problem with the supplies, and as a byproduct, when the power is going up.

Eli

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alessandro basili 19 years ago

Could you please give me a reference for those?

thanks a lot

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Al 19 years ago

Excuse me Eli, can you give me a reference for those tiny ICs? thanks a lot

Alessandro Basili CERN, PH/UGC Hardware Designer

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Eli Bendersky 19 years ago

Hello Al,

Googling "voltage supervisor" will bring up lots of results

Eli

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