Altera or Xilinx

You are right the ispLever tools do include VHDL. I somehow missed that, sorry for the mis-information there.

My wording may be a little unflatering, but I think that it's true for low/medium-end designs. The real differences only show up when you want to get the most out of these devices. Thats why I added the specific designs exeption, there will be designs where it does matter.

I started this thread by asking for the differences and got no replies that stated clear diffrences. From that I concluded that there's not much between them, and is this not true for simple(r) designs?

I'm an Alfa Romeo adept myself, so BMW or Mercedes have no real differences between them (to me).

The interesting and important stuff is mostly only required for high- end stuff. I need 10-40Mbps IO, not 3GBs, only a few kB of memory, some state machines that run in the 10-100MHz range, not rocket science.

Not if you're only looking for a bit of water and some rocks, if you're interested in nice scenery then yes.

I would also try to evaluate the technical support that you'll receive.

The FAE support I get from EBV here in the UK for Altera devices is second to none.

Nial.

Heard that with ispLever 7.0 they now also support mixed VHDL/Verilog design which Altera is doing it for years now (o;

Can someone confirm on this?

cheers rick

Just for the record: That delay was some miscommunication.

If possible, yes. But evaluating support is not the easiest job. ;-)

I've already talked to an Altera FAE and he seemded OK. The real test is ofcourse supporting real design problems/questions.

Well he is waiting for you to really start designing ;-)

Karl.

PS: I do not drive an Alfa

Yes, I know he is. 8-)

What do you drive?

Yes, Lattice ispLEVER 7.0 does support mixed VHDL / Verilog synthesis native to the ispLEVER Project Navigator GUI. Actually, the ispLEVER has supported a mixed language support for some time. In the past, Precsion (included with the ispLEVER) could be used as the synthesis vendor of choice to create an EDIF file from a mixed design. Then the EDIF file could be brought into the ispLEVER Project Navigator. The advantage of ispLEVER 7.0 is that now a "single-step" flow can be supported and customers can use Synplify as a synthesis tool if so desired.

John Dimtsios Lattice

If you aren't pushing performance, power, or price and don't care about any particular software feature, any chip will probably do. But I would contend (perhaps even agree with Peter) that there are significant differences between Altera and Xilinx's products. I would suggest you sit down, take a quick inventory of what you need from your FPGA device, decide whether you fit in the low-cost (Cyclone / Spartan) or high-end (Stratix / Virtex) space, and then start comparing device features. Talk to a sales rep from each company to find out price. Download the free software and kick the tires a little and see what you like. And read some literature / marketing stuff on device performance and power.

And Peter, the answer is clearly Canada :-)

Regards,

Paul Leventis Altera CANADA Corp.

Of course, Paul. I thought of you when I wrote it... Cheers Peter

Requirements are very modest and will fit with ease in the lowest cost chips.

Got prices for both. Talked to one FAE, the other one is on holiday. I've ordered the low-cost dev-kit from both. I'll go through at least the first sample designs (led blink?) to get a feel for both. Have not checked power yet, will do when I get the boards.

let me step into this discussion - because i also wanna start working with FPGA and i am still not sure, which device/board to use (buy). First i was favouring Altera/Terasic TREX or DE1 board. Then i discussed with s.o., who is using Xilinx FPGAs, and he told me, that Xilinx is providing development kits for linux (ISE&EDK) - whereas Altera doesn't. This sounded nice to me, because i am working with linux. My idea is to use SystemC & gscc writing or re-designing application in CSP-style and targeting a dedicated process to FPGA then.

But now my problem: for this i need FPGA board and development kit, which provides some useful (data) IF between a host system (PC) and the FPGA board for streaming data to FPGA (for fast processing) and results back to PC (after having programmed/configured the FPGA). In an ideal world some IF, which can be easily integrated with SystemC (e.g.). I was "assuming" that the FPGA manufacturers development tools provide such (for demo application, etc). Many boards have USB IF, some ethernet.

Does anybody have experiences using SystemC, ISE/EDK for CSP-style programming with targeting dedicated processes to FPGA, while the rest is working on linux PC?

Frank

voted as the best FPGA poem :-)

The different devices have different features. As a result a design for the same end purpose executed in an Altera device may be very different from a design executed in a Xilinx device. This is particularly true if you are pushing the performance or density envelopes.

An example of this is a design that needs many very small memories (short reorder queues for example) might be considerably more compact in Xilinx by taking advantage of the SRL16 primitives. A design with strictly 8 or 9 bit arithmetic and lots of multiplies might be a better fit to Altera Stratix because of it's 9x9 multipliers.

It isn't a matter of one device being unsuitable as much as it is an issue of one device being better suited.

Ray's point hit it on the head. Be aware however, that you need to actually power and cool the resulting design too. Many SRL16's in a design may lead to interesting data dependent power issues and cooling problems at best case clock rates.

If FCS dates are critical to company success, you might consider prototyping both vendors solutions early, and once you have working designs let the price/availability shoot out occur. Avoids late discoveries about suitability, and leaves open vendor choices longer, while impacting the R&D budget less than a few percent for most larger projects.