ADCs in FPGAs

It is also going to be dependent on the tolerances of the other parts - the resistors, capacitors, buffers.

There are also lots of microcontrollers with quite reasonable multi-channel ADC's and lower prices than this. They are usually not so good for high resolution, but you can do other things with the microcontroller too.

And for higher resolution requirements, the effort to make your own and be sure it is accurate would seem ridiculous. How many hundreds of thousands of systems are you making where the development costs of rolling your own ADC, testing and qualifying it save the cost of buying one?

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David Brown
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Sounds like best of both worlds.

That's still only a few mV of noise threshold.

I might use a standard comparator rather than rely on an input with a noisy threshold. Not mentioning the violation of rise times.

My experience of off-board third party digital sensors isn't a happy one with I2C sensors locking up on a glitch and having to reset them on the fly.

YMMV

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Mike Perkins

Anyone know if that is actually an ADC or if it is an ADC chip interface?

s.

ntiated "IP" but I suppose that might be the same as "instantiating" a cloc k block with PLL ect.

and the real issue is how much he knows about delta-sigma converters and ho w to implement them.

mprove accuracy and/or noise to use separate comparator and driver for the analog interface. The sensors are powered from 5 volts and so produce a 5 volt analog output. The separate drivers and comparators could be powered from the same supply, separate from any other supply on the board for noise isolation. Also, as the sensor outputs are proportional to the power rail voltage, this will make all measurements ratiometric eliminating the need to correct for the power voltages. Otherwise we need to provide the I/O ba nk 3.3 volts that is a ratioed to the 5 volt rail. I guess no big deal. Th e point is it's not that much more to use separate comparators and drivers and may get us noise and accuracy advantages.

idify my thinking. In this case we have tons of I/Os available, so I think I'm going to use both approaches and dedicate a bank of I/Os to the ADCs.

ltiple channels are in the $5 and up range. I can get comparators for a qu arter and CMOS buffers for a dime. I'm not sure the comparators are needed . The buffer might help though.

Which aspects of the FPGA impact the performance of a delta-sigma ADC? Or even a single slope ADC? The only relevant aspect would be the voltage dro p from Vcc/ground to the output drive which is going to be very small when driving low currents.

As I said, there will be an ADC on board for testing. Then we will choose the method that works best for our goals.

No risk, no worries.

If anything, having the delta-sigma ADC as a backup to the chip ADC reduces the risk if there is a glitch with the chip. It's not like ICs never have problems.

$0.10 is still a lot better than $3.50.

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  Rick C. 

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Rick C

I've been messing with this for a bit and the ultimate limitation seems to me to not be the digital noise in the FPGA, but rather the imbalance in the edge rise/fall times and/or propagation delays.

The digital noise in the FPGA is going to be mostly in the core. The I/Os a re the part that matter to the analog portion of the ADC and they have sepa rate Vcco from the core and also one another. I've been planning to dedicat e a bank to the ADCs. But the input signals have a 5 volt range and will re quire a 3.3 Vcco that is ratiometric to the 5 volt supply. It seems simpler to add a 5 volt level shifter and let that be powered by the sensor 5 volt rail.

So now I'm looking for the right buffer device and I'm starting to realize the limitation is the symmetry in the rise/fall times and the propagation d elays of the two edges. Buffers are not so good with this having delays of single digit ns, but also lack of symmetry of single digit ns. With 30 ns p ulses, that would add up. I thought analog switches might be better, but th ey are worse with unbalanced switching times being hard to get into the low single digit ns. Many of the parts I find are LVC which require 3.3 volt p ower to get compatible input levels. I guess that's what the L is for in L VC, duh!

Anyone know of parts that would be good for this? Would it make sense to ru n through two buffers at least conceptually balancing the rise/fall times a nd prop delays? But then the delays start to add up, but that probably does n't matter as much.

I found the 74ACT244 which seems to be the best fit so far. 5V power, TTL inputs to be compatible with 3.3V CMOS, balanced HL and LH propagation time s and balanced H and L drive capabilities. The prop delay can be up to 9 n s which is a significant portion of the 30 ns cycle time, but that should n ot be a significant factor.

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