A fast 100k:1 ratio timer

In an analog circuit, I have a line that drives something wicked fast, and needed to ensure the load device disconnects after a non-critical timeout period.

+5V Q1 -+- MMBT4401 | .-----------. \ ^ |

--. ----- Rt | .--- | | 2.2M | |\ | 0|O-----+--/\/\/---+----/\/\/-----+-----| >o-----O|EN | | R1 | |/ | U1 | 330 Ct --- U2 |

74LVC139 | 4.7n --- 74AHCT14 | LOAD tpd=2nS | | | (typ) | === | | | '----------------------------------------O|CS | '--- OPERATION

Quiescent Normally U1.0 = high, Ct is fully charged, and EN=low. Idling 'enabled' avoids any excess delay when CS* comes along later.

Active U1.0 selects the load by driving CS* low. Ct begins discharging through Rt, forming a timer.

Timeout Normally U1.0 will go high within 50nS < t < 2mS. Should it linger low ~>=10mS, Ct discharges & U2's output goes high, disabling the load.

Recovery Recovery < 100nS is desired. Since the timing current is

2.5uA, the reset current needs to be at least 10mS/100nS = 100k * 2.5uA = 250mA.

U1 drives 32mA--not shabby, but not enough to drive a diode across Rt. Also, we don't want to slow the critical signal path to CS* during normal operation.

Q1, then, boosts U1's output to ~400mA, effecting a prompt reset.

(I fiddled with timer ideas using the usual suspect ICs, but none of them had both a fast enough response, and a high enough reset-to-timing current ratio.)

Cheers, James Arthur

Reply to
dagmargoodboat
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WRT your fast-recovery feature. This looks to be protective against programming faults, etc., that fail to turn off the load fast enough. But with a super-fast recovery, if the same event, with its error, is tried again shortly thereafter, repeated full timeouts could defeat the desired protection. In contrast, see Fig 7.63 in AoE III, page 466. This circuit has a timer that enforces a lockout time for each load pulse, insuring that some safe maximum duty cycle cannot be exceeded.

--
 Thanks, 
    - Win
Reply to
Winfield Hill

Thanks Win.

That circuit's lockout feature prevents re-firing pulses for the duration of the lockout time, thus enforcing a max duty cycle.

This requirement is a bit different.

Here the '139, responding to an external sequencer, fires bursts of

50nS...2mS pulses on its four outputs, driving four load sections. Even idling, then, one load section will still be selected.

The aim here is to deactivate all the loads in-between those bursts (so that we don't have one channel at 100% duty), yet be able to re-start bursting sequences with minimal delay.

In-between bursts at least one of the four channel's timers will have timed out, and will require a reset delay time before its channel can be used again.

Any reset delay >0 means the customer has to insert dummy pulses to accommodate the timer circuit's reset / enable time. 100nS (two minimum pulse periods) is fine, 50nS would be even better, 0nS would be better still :-).

Using a Schmitt with lower Vin(h) helps--the load is enabled earlier in the reset (Ct-charging) cycle than it otherwise would be.

Cheers, James Arthur

Reply to
dagmargoodboat

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