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Question about HP 16500 sampling

I'm using an HP 16500A in the lab and was wondering about how this unit samples. Each pod seems to have a clock and it looks like from the menus that you can assign a clock to capture events. But that limits me to the fastest clock on the board, which is the system clock. In order for these waveforms to accurately represent what is going on I should be sampling at least 2x this rate. So does the unit had an internal async adjustable sample rate like some other LA's I've seen?

Trigger off of an event and then just sample every N ns........ etc

Thanks,

-Adam ===============

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Reply to
ajcrm125
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Hi Adam,

It could depends on the acquisition card you have in your 16500, but as far as I know the large majority of the 16500's serie logic analyser boards provides both a "state analysis" mode (meaning clocked from a clock signal from your board as you explained) as well as a "timing analysis" mode (meaning clocked from an independant, asynchronous clock). For example the

16555A allows state analysis up 110MHz and timing analysis up to 500MHz. You can change the state/timing mode from the configuration menu. Moreover in "state analysis" some boards (as the 16555) allows you to time-stamp the clock events as well.

However you may be wrong when you state that you need "2x the highest clock rate" as for example if you are interested in the functionnal behaviour of your device then you only need to sample once per clock cycle (ie state mode).

Cheers, Robert

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Reply to
Robert Lacoste

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