x86 TLB and cache for page directory

For x86 ,as we know ,page directory and page table can be cached in TLB,but it can also be cached in data cache accordding to whether pcd is clear in cr3.What's the relationship between TLB and data cache for page directory if pcd is clear in cr3?How the processor to access the TLB and data cache if the page directory is not in TLB but in data cache?