What is happening to Atmel EEPROMs?

The LP17xx series require flash wait states when run at speeds over 20 MHz. When running at full speed four wait states must be inserted (see the description of the FLASHCFG register, p. 71 in the user manual). The chips do have a flash accelerator (a tiny, simple cache really) to help hide the latency.

-a

Jon Kirwan skrev:

If you read a 128 bit word, and then you turn off the chip select, you are going to face extra waitstates when you do a jump. That is why you do not turn off the flash at high speed.

If you run at low speed, you can turn off the flash, if you can guarantee that the flash is on again, at the beginning of the next clock.

CLK ______|"""""""""""""""""""""""""|______________________|"""""""""

/CS """"\______________/"""""""""""""""""""""""""""""""\______________/

DATA -----------------------------------------------

When you run at high speeds, you do not have any clock edges to start the chip select, and you do not want to wait until you do a jump to enable the chip selects, since that adds wait states.

You cant do it when your flash access cycle is close to your bus cycle. It only make sense if the flash access is much faster than your clock cycle.

No, Atmel does not turn off the flash, when running at SAM3/7 at 50-60 MHz.

See above. BR Ulf Samuelsson

I have done some measurements on CM3 using Dhrystone 2.1 & Keil, and you get the following Dhrystone 2.1 MIPS / MHz.

64 bit 128 bit 0 waitstate 1,223 1,223 1 waitstate 1,068 1,107 2 waitstate 0,915 0,998 3 waitstate 0,774 0,861 4 waitstate 0,660 0,749

based on this, an LPC17xxx running at 100 Mhz w 4 waitstates on non-sequential fetch would run around 75 MIPS or ~61 % of the performance of the zero waitstate memory.

Adding one waitstate extra latency on non-sequential fetch removes about 10-15% of the performance from the otherwise zero waitstate.

BR Ulf Samuelsson

I have done some measurements on CM3 using Dhrystone 2.1 & Keil, and you get the following Dhrystone 2.1 MIPS / MHz.

64 bit 128 bit 0 waitstate 1,223 1,223 1 waitstate 1,068 1,107 2 waitstate 0,915 0,998 3 waitstate 0,774 0,861 4 waitstate 0,660 0,749

based on this, an LPC17xxx running at 100 Mhz w 4 waitstates on non-sequential fetch would run around 75 MIPS or ~61 % of the performance of the zero waitstate memory.

Adding one waitstate extra latency on non-sequential fetch removes about 10-15% of the performance from the otherwise zero waitstate.

BR Ulf Samuelsson

none=20

Thanks. If i weren't distracted i might have provided a similar link.