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Reading from a NAND

Hi,

I'm currently implementing a new Nand Interface on our hardware.

The old interface has a register that accepts the complete address and thus keep ALE high between the individual bytes that it clocks out. The NAND can thus know that it has the complete address when ALE goes low and should start the 'read' at this point.

The new interface requires each address byte to be written to the register separately and thus doesn't necessarily know when it has the final byte. This leads me to suspect (I don't yet have working HW to check) that ALE goes low between each individual byte, so the NAND won't have an indicator from the interface that the address is complete.

Of course, the NAND could work out for itself when it has the complete address and start the 'read' then, but does it?

Does anyone know how this part of the interface actually works?

TIA

Tim

Reply to
tim (moved to sweden)
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On Thu, 8 Sep 2005 22:27:24 +0200, "tim \(moved to sweden\)" wrote in comp.arch.embedded:

It may just be me, but your post seems to be missing a lot of information.

Do you mean NAND flash memory, or something else?

Are you talking about a NAND flash with a multiplexed address bus or address/data bus? I don't know of any, but I suppose some might exist. Otherwise, I don't understand your mention of ALE in this context.

Again, I don't know what ALE has to do with anything.

Every parallel interface flash memory that I am familiar with, which is by no means all of them, has some sort of chip select pin (usually labeled /CS or /CE), and some sort of output or read enable pin (usually /OE or /RD).

On the other hand, if you are not talking about flash memory, perhaps you had better post again and provide more detail. I've heard of NAND gates and NAND flash, don't remember anything just called 'a NAND'.

--
Jack Klein
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Reply to
Jack Klein

ALE does not have to remain high during the entire address cycle, at least on Samsung parts. From the selection of data sheets that I have, the NAND flash "knows" how many address bytes are required. Andrew

Reply to
Andrew Jackson

Mea culpa, I could have meant Nand gate?

Isn't this an inherent feature of the type? All the things that I have read on NAND works on the assumption that there are no address lines. All the stuff about it being impossible to execute in place, having bad block management etc. If this were just about reducing pin count there could have been NOR flashes with no address lines.

I've no idea what it is about the technology that caused it be be designed this way in the first place, but ISTM that if someone were to market a 'NAND' with address lines it would have to be given a different name.

Becuse ALE tells the flash when the address part of the 'command' is being transmitted.

And it is (was) the operation of this line that interested me.

I have my answer now thanks.

tim

Reply to
tim (moved to sweden)

Ta very much,

Just the answer that I was looking for.

tim

Reply to
tim (moved to sweden)

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