Hi,
my design is a cache module. In order to have a required cache throughput, it is necessary for me to be able to read a cache line tag and set the dirty bit of another cache line tag in the same cycle.
This would require me to have a dual-port RAM for the Tag memories, BUT 'higher powers' consider that a DP memory is too costly area-wise... so the decision was made to have the dirty bits of the tags implemented separately in registers.
My question is, does this really make sense? I mean the registers take in more area than RAM and a additional 'address' decoding logic is still necessary.
Regards, Ernest