PCIe controller in congatec SMX8 does not work

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I try to get PCIe working in congatec SMX8 connected to the conga-SKIT/ARM i.MX8 motherboard.
I use it with XTRX software radio module from Fairwaves.  
Unfortunately, the PCIe controller does not start both with XTRX connected directly to MiniPCIe slot and with XTRX connected via original adapter to the M2 slot.

I get the following in the dmesg:

    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.14.98-cgt_4.14.98_2.2.0+ge5f132f (oe-user@oe-host
) (gcc version 7.3.0 (GCC)) #1 SMP PREEMPT Thu Nov 21 15:01:20 UTC 2019
[    0.000000] Boot CPU: AArch64 Processor [410fd034]
[    0.000000] Machine model: congatec SMX8
[...]
[    1.100004] imx6q-pcie 5f000000.pcie: 5f000000.pcie supply epdev_on not found, using dummy regulator
[    1.109047] OF: PCI: host bridge /pcie@0x5f000000 ranges:
[    1.114199] OF: PCI:   No bus range found for /pcie@0x5f000000, using [bus 00-ff]
[    1.121676] OF: PCI:    IO 0x6ff80000..0x6ff8ffff -> 0x00000000
[    1.127581] OF: PCI:   MEM 0x60000000..0x6fefffff -> 0x60000000
[    1.134720] imx6q-pcie 5f000000.pcie: pcie phy pll is locked.
[    1.385299] imx6q-pcie 5f000000.pcie: phy link never came up
[    1.390631] imx6q-pcie 5f000000.pcie: failed to initialize host
[    1.396528] imx6q-pcie 5f000000.pcie: unable to add pcie port.
[    1.402529] imx6q-pcie: probe of 5f000000.pcie failed with error -110

Of course, lspci does not report any devices later on.

I use the original Linux image provided by congatec.

I'll appreciate any hints ort suggestions.
With best regards,
Wojtek

Re: PCIe controller in congatec SMX8 does not work
snipped-for-privacy@gmail.com wrote:
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That suggests the clock is there but the PHY couldn't bring the link up, or
it couldn't detect the other end bringing up their side.
  
Does the PHY need power gating in some way?  Do you need to enable power to
the PCIe slot?  Do you need to pinmux the PCIe pins (probably not)?  Are the
clock settings correct?

I'm curious what the first line means, as it suggests it couldn't find a way
to turn power on.

Can you look for a known-good device tree and see if there's anything
missing from yours?

I'm assuming you have a miniPCIe card that actually does PCIe, as opposed to
a card that's only USB (eg most WWAN cards)?  Ah, I found the XTRX - it does
PCIe in an FPGA as well as USB.  I think you then need to program the FPGA
(via flash?) before booting the system, since an empty FPGA will not
bring up the PCIe link.

Theo

Re: PCIe controller in congatec SMX8 does not work
W dniu pi?tek, 27 marca 2020 13:05:54 UTC+1 u?ytkownik Theo napis
a?:
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ARM i.MX8 motherboard.
Quoted text here. Click to load it
ted directly to MiniPCIe slot and with XTRX connected via original adapter  
to the M2 slot.
Quoted text here. Click to load it
not found, using dummy regulator
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g [bus 00-ff]
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or
to
the
way
 to
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oes
A

Thanks for your reply and suggestions. I have put XTRX to the miniPCIe slot
 in Orange Pi RK3399 and it works immediately:

01:00.0 Memory controller: Xilinx Corporation Device 7012
        Subsystem: Xilinx Corporation Device 0007
        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
 Stepping- SERR- FastB-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <T
Abort- <MAbort- >SERR- <-
        Interrupt: pin A routed to IRQ 226
        Region 0: Memory at fa010000 (32-bit, non-prefetchable) [disabled]  
[size=4K]
        Region 1: Memory at fa000000 (32-bit, non-prefetchable) [disabled]  
[size64%K]
        Capabilities: [40] Power Management version 3
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2
+,D3hot+,D3cold-)
                Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
        Capabilities: [48] MSI: Enable- Count=1/16 Maskable- 64bit+
                Address: 0000000000000000  Data: 0000
        Capabilities: [60] Express (v2) Endpoint, MSI 01
                DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64n
s, L1 unlimited
                        ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- Slo
tPowerLimit 0.000W
                DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsup
ported-
                        RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
                        MaxPayload 128 bytes, MaxReadReq 512 bytes
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- Tr
ansPend-
                LnkCap: Port #0, Speed 5GT/s, Width x2, ASPM L0s, Exit Late
ncy L0s unlimited, L1 d
                        ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLA
ctive- BWMgmt- ABWMgmt-
                DevCap2: Completion Timeout: Range B, TimeoutDis-, LTR-, OB
FF Not Supported
                DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR
-, OBFF Disabled
                LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDi
s-
                         Transmit Margin: Normal Operating Range, EnterModi
fiedCompliance- Compli-
                         Compliance De-emphasis: -6dB
                LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationCom
plete-, EqualizationPh-
                         EqualizationPhase2-, EqualizationPhase3-, LinkEqua
lizationRequest-
        Capabilities: [100 v1] Device Serial Number 00-00-00-00-12-34-56-78

So the FPGA is programmed from the FLASH.
Indeed, the problem may be related to the DT. Unfortunately I do not have a
ny other DT than the one downloaded from the system I'm trying to start via

root@imx8qm-cgtsmx8:~# cat /sys/firmware/fdt > /tmp/imx8.dtb
and then on the host:
 dtc -I dtb -O dts -o imx8.dts < imx8.dtb

    pcie@0x5f000000 {
        compatible = "fsl,imx8qm-pciesnps,dw-pcie";
        reg = <0x00 0x5f000000 0x00 0x10000 0x00 0x6ff00000 0x00 0x80000>;
        reg-names = "dbiconfig";
        reserved-region = <0x141>;
        #address-cells = <0x03>;
        #size-cells = <0x02>;
        device_type = "pci";
        ranges = <0x81000000 0x00 0x00 0x00 0x6ff80000 0x00 0x10000 0x82000000  
0x00 0x60000000 0x00 0x60000000 0x00 0xff00000>;
        num-lanes = <0x01>;
        #interrupt-cells = <0x01>;
        interrupts = <0x00 0x46 0x04 0x00 0x48 0x04>;
        interrupt-names = "msi";
        clocks = <0x03 0x1fd 0x03 0x1fe 0x03 0x20f 0x03 0x204 0x03 0x1ff>;
        clock-names = "pciepcie_buspcie_phypcie_perpcie_inbound_axi";
        interrupt-map-mask = <0x00 0x00 0x00 0x07>;
        interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x49 0x04 0x00 0x00 0x00
 0x02 0x01 0x00 0x4a 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x4b 0x04 0x00 0x00
 0x00 0x04 0x01 0x00 0x4c 0x04>;
        power-domains = <0x21>;
        fsl,max-link-speed = <0x03>;
        hsio-cfg = <0x02>;
        hsio = <0x142>;
        ctrl-id = <0x00>;
        cpu-base-addr = <0x40000000>;
        status = "okay";
        ext_osc = <0x01>;
        pinctrl-names = "default";
        pinctrl-0 = <0x143>;
        reset-gpio = <0x114 0x1d 0x01>;
        clkreq-gpio = <0x114 0x1b 0x01>;
    };

    pcie@0x5f010000 {
        compatible = "fsl,imx8qm-pciesnps,dw-pcie";
        reg = <0x00 0x5f010000 0x00 0x10000 0x00 0x7ff00000 0x00 0x80000>;
        reg-names = "dbiconfig";
        reserved-region = <0x141>;
        #address-cells = <0x03>;
        #size-cells = <0x02>;
        device_type = "pci";
        ranges = <0x81000000 0x00 0x00 0x00 0x7ff80000 0x00 0x10000 0x82000000  
0x00 0x70000000 0x00 0x70000000 0x00 0xff00000>;
        num-lanes = <0x01>;
        #interrupt-cells = <0x01>;
        interrupts = <0x00 0x66 0x04 0x00 0x68 0x04>;
        interrupt-names = "msi";
        clocks = <0x03 0x200 0x03 0x201 0x03 0x210 0x03 0x203 0x03 0x202>;
        clock-names = "pciepcie_buspcie_phypcie_perpcie_inbound_axi";
        interrupt-map-mask = <0x00 0x00 0x00 0x07>;
        interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x69 0x04 0x00 0x00 0x00
 0x02 0x01 0x00 0x6a 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x6b 0x04 0x00 0x00
 0x00 0x04 0x01 0x00 0x6c 0x04>;
        power-domains = <0x21>;
        fsl,max-link-speed = <0x03>;
        hsio-cfg = <0x02>;
        hsio = <0x142>;
        ctrl-id = <0x01>;
        cpu-base-addr = <0x80000000>;
        status = "disabled";
        ext_osc = <0x01>;
        pinctrl-names = "default";
        pinctrl-0 = <0x144>;
        clkreq-gpio = <0x114 0x1e 0x01>;
    };

The strange thing is that both controllers are configured to have only a si
ngle lane.
I know that there are four lanes conencted on the board.

Re: PCIe controller in congatec SMX8 does not work
OK. I have found a solution. I obtained the information that in Conga SMX8 the M2 PCIe port is connected to the PCIe_B lines, and MiniPCIe port is connected to the PICe_C lines.
In my decompiled device tree I have found:

    pcie@0x5f000000 {
        compatible = "fsl,imx8qm-pciesnps,dw-pcie";
        reg = <0x00 0x5f000000 0x00 0x10000 0x00 0x6ff00000 0x00 0x80000>;
        reg-names = "dbiconfig";
        reserved-region = <0x141>;
        #address-cells = <0x03>;
        #size-cells = <0x02>;
        device_type = "pci";
        ranges = <0x81000000 0x00 0x00 0x00 0x6ff80000 0x00 0x10000 0x82000000 0x00 0x60000000 0x00 0x60000000 0x00 0xff00000>;
        num-lanes = <0x01>;
        #interrupt-cells = <0x01>;
        interrupts = <0x00 0x46 0x04 0x00 0x48 0x04>;
        interrupt-names = "msi";
        clocks = <0x03 0x1fd 0x03 0x1fe 0x03 0x20f 0x03 0x204 0x03 0x1ff>;
        clock-names = "pciepcie_buspcie_phypcie_perpcie_inbound_axi";
        interrupt-map-mask = <0x00 0x00 0x00 0x07>;
        interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x49 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x4a 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x4b 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x4c 0x04>;
        power-domains = <0x21>;
        fsl,max-link-speed = <0x03>;
        hsio-cfg = <0x02>;
        hsio = <0x142>;
        ctrl-id = <0x00>;
        cpu-base-addr = <0x40000000>;
        status = "okay";
        ext_osc = <0x01>;
        pinctrl-names = "default";
        pinctrl-0 = <0x143>;
        reset-gpio = <0x114 0x1d 0x01>;
        clkreq-gpio = <0x114 0x1b 0x01>;
    };

    pcie@0x5f010000 {
        compatible = "fsl,imx8qm-pciesnps,dw-pcie";
        reg = <0x00 0x5f010000 0x00 0x10000 0x00 0x7ff00000 0x00 0x80000>;
        reg-names = "dbiconfig";
        reserved-region = <0x141>;
        #address-cells = <0x03>;
        #size-cells = <0x02>;
        device_type = "pci";
        ranges = <0x81000000 0x00 0x00 0x00 0x7ff80000 0x00 0x10000 0x82000000 0x00 0x70000000 0x00 0x70000000 0x00 0xff00000>;
        num-lanes = <0x01>;
        #interrupt-cells = <0x01>;
        interrupts = <0x00 0x66 0x04 0x00 0x68 0x04>;
        interrupt-names = "msi";
        clocks = <0x03 0x200 0x03 0x201 0x03 0x210 0x03 0x203 0x03 0x202>;
        clock-names = "pciepcie_buspcie_phypcie_perpcie_inbound_axi";
        interrupt-map-mask = <0x00 0x00 0x00 0x07>;
        interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x69 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x6a 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x6b 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x6c 0x04>;
        power-domains = <0x21>;
        fsl,max-link-speed = <0x03>;
        hsio-cfg = <0x02>;
        hsio = <0x142>;
        ctrl-id = <0x01>;
        cpu-base-addr = <0x80000000>;
        status = "disabled";
        ext_osc = <0x01>;
        pinctrl-names = "default";
        pinctrl-0 = <0x144>;
        clkreq-gpio = <0x114 0x1e 0x01>;
    };

            pcieagrp {
                fsl,pins = <0xc6 0x03 0x21 0xc7 0x03 0x21 0xc8 0x03 0x21>;
                linux,phandle = <0x143>;
                phandle = <0x143>;
            };

            pciebgrp {
                fsl,pins = <0xc9 0x03 0x21 0xca 0x03 0x21 0xcb 0x03 0x21>;
                linux,phandle = <0x144>;
                phandle = <0x144>;
            };

So it is clear, that the PCIe controller at 0x5f000000 is connected to port A, while the PCIe controller at 0x5f010000 is connected to port B.

Therefore, I have moved the XTRX module to the M2 PCIe port (using the adapter that was delivered together with XTRX), switched off the controller at 0x5f000000, and switched on the controller at 0x5f01000.
Changing the active controller was done in U-Boot:

run loadfdt; fdt adr $fdt_addr ; fdt resize
fdt set /pcie@0x5f000000 status disabled
fdt set /pcie@0x5f010000 status okay    
run mmcargs; run loadimage ; run boot_os

After the above, the system booted correctly, and I could see the below messages.

In the boot log:
[    1.131045] imx6q-pcie 5f010000.pcie: 5f010000.pcie supply epdev_on not found, using dummy regulator
[    1.140117] OF: PCI: host bridge /pcie@0x5f010000 ranges:
[    1.145238] OF: PCI:   No bus range found for /pcie@0x5f010000, using [bus 00-ff]
[    1.152716] OF: PCI:    IO 0x7ff80000..0x7ff8ffff -> 0x00000000
[    1.158615] OF: PCI:   MEM 0x70000000..0x7fefffff -> 0x70000000
[    1.165678] imx6q-pcie 5f010000.pcie: pcie phy pll is locked.
[    1.186275] imx6q-pcie 5f010000.pcie: Link up, Gen2
[    1.191791] imx6q-pcie 5f010000.pcie: PCI host bridge to bus 0000:00
[    1.197815] pci_bus 0000:00: root bus resource [bus 00-ff]
[    1.203277] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
[    1.209444] pci_bus 0000:00: root bus resource [mem 0x70000000-0x7fefffff]
[    1.226960] pci 0000:00:00.0: BAR 0: assigned [mem 0x70000000-0x70ffffff 64bit]
[    1.233945] pci 0000:00:00.0: BAR 6: assigned [mem 0x71000000-0x71ffffff pref]
[    1.241151] pci 0000:00:00.0: BAR 14: assigned [mem 0x72000000-0x720fffff]
[    1.248019] pci 0000:01:00.0: BAR 1: assigned [mem 0x72000000-0x7200ffff]
[    1.254797] pci 0000:01:00.0: BAR 0: assigned [mem 0x72010000-0x72010fff]
[    1.261581] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[    1.266773] pci 0000:00:00.0:   bridge window [mem 0x72000000-0x720fffff]
[    1.274430] pcieport 0000:00:00.0: Signaling PME with IRQ 413
[    1.279946] pcieport 0000:00:00.0: AER enabled with IRQ 414

And as the output of the lspci:

root@imx8qm-cgtsmx8:~# lspci -v -v
00:00.0 PCI bridge: Freescale Semiconductor Inc Device 0000 (rev 01) (prog-if 00 [Normal decode])
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 0
        Interrupt: pin A routed to IRQ 413
        Region 0: Memory at 70000000 (64-bit, non-prefetchable) [size16%M]
        Bus: primary00%, secondary01%, subordinate=ff, sec-latency=0
        I/O behind bridge: None
        Memory behind bridge: 72000000-720fffff [size=1M]
        Prefetchable memory behind bridge: None
        Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
        [virtual] Expansion ROM at 71000000 [disabled] [size16%M]
        BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
                PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
        Capabilities: [40] Power Management version 3
                Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
        Capabilities: [50] MSI: Enable+ Count=2/16 Maskable- 64bit+
                Address: 0000000096040000  Data: 0000
        Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00
                DevCap: MaxPayload 256 bytes, PhantFunc 0
                        ExtTag- RBE+
                DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
                        RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
                        MaxPayload 128 bytes, MaxReadReq 512 bytes
                DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
                LnkCap: Port #0, Speed 8GT/s, Width x1, ASPM L0s, Exit Latency L0s unlimited
                        ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
                LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk+
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt+
                RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible-
                RootCap: CRSVisible-
                RootSta: PME ReqID 0000, PMEStatus- PMEPending-
                DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd-
                         AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
                DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
                         AtomicOpsCtl: ReqEn- EgressBlck-
                LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
                         Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
                         Compliance De-emphasis: -6dB
                LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
                         EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
        Capabilities: [100 v2] Advanced Error Reporting
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
                UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout+ NonFatalErr-
                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
                AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
                        MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
                HeaderLog: 00000000 00000000 00000000 00000000
                RootCmd: CERptEn+ NFERptEn+ FERptEn+
                RootSta: CERcvd+ MultCERcvd- UERcvd- MultUERcvd-
                         FirstFatal- NonFatalMsg- FatalMsg- IntMsg 1
                ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000
        Capabilities: [148 v1] #19
        Capabilities: [168 v1] L1 PM Substates
                L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ L1_PM_Substates+
                          PortCommonModeRestoreTime10%us PortTPowerOnTime10%us
                L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
                           T_CommonMode10%us
                L1SubCtl2: T_PwrOn10%us
        Kernel driver in use: pcieport

01:00.0 Memory controller: Xilinx Corporation Device 7012
        Subsystem: Xilinx Corporation Device 0007
        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Interrupt: pin A routed to IRQ 255
        Region 0: Memory at 72010000 (32-bit, non-prefetchable) [disabled] [size=4K]
        Region 1: Memory at 72000000 (32-bit, non-prefetchable) [disabled] [size64%K]
        Capabilities: [40] Power Management version 3
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
                Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
        Capabilities: [48] MSI: Enable- Count=1/16 Maskable- 64bit+
                Address: 0000000000000000  Data: 0000
        Capabilities: [60] Express (v2) Endpoint, MSI 01
                DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 unlimited
                        ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0.000W
                DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
                        RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
                        MaxPayload 128 bytes, MaxReadReq 512 bytes
                DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
                LnkCap: Port #0, Speed 5GT/s, Width x2, ASPM L0s, Exit Latency L0s unlimited
                        ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
                DevCap2: Completion Timeout: Range B, TimeoutDis-, LTR-, OBFF Not Supported
                         AtomicOpsCap: 32bit- 64bit- 128bitCAS-
                DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
                         AtomicOpsCtl: ReqEn-
                LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
                         Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
                         Compliance De-emphasis: -6dB
                LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
                         EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
        Capabilities: [100 v1] Device Serial Number 00-00-00-00-12-34-56-78

So now the next question is - how to enable the port C (as using the board directly, not via an adapter, is much more safe and convenient).

BR,
Wojtek

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