PCIe controller in congatec SMX8 does not work

That suggests the clock is there but the PHY couldn't bring the link up, or it couldn't detect the other end bringing up their side. Does the PHY need power gating in some way? Do you need to enable power to the PCIe slot? Do you need to pinmux the PCIe pins (probably not)? Are the clock settings correct?

I'm curious what the first line means, as it suggests it couldn't find a way to turn power on.

Can you look for a known-good device tree and see if there's anything missing from yours?

I'm assuming you have a miniPCIe card that actually does PCIe, as opposed to a card that's only USB (eg most WWAN cards)? Ah, I found the XTRX - it does PCIe in an FPGA as well as USB. I think you then need to program the FPGA (via flash?) before booting the system, since an empty FPGA will not bring up the PCIe link.

Theo

ARM i.MX8 motherboard.

ted directly to MiniPCIe slot and with XTRX connected via original adapter to the M2 slot.

not found, using dummy regulator

g [bus 00-ff]

or

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Thanks for your reply and suggestions. I have put XTRX to the miniPCIe slot in Orange Pi RK3399 and it works immediately:

OK. I have found a solution. I obtained the information that in Conga SMX8 the M2 PCIe port is connected to the PCIe_B lines, and MiniPCIe port is connected to the PICe_C lines. In my decompiled device tree I have found:

pcie@0x5f000000 { compatible = "fsl,imx8qm-pcie\0snps,dw-pcie"; reg = ; reg-names = "dbi\0config"; reserved-region = ; #address-cells = ; #size-cells = ; device_type = "pci"; ranges = ; num-lanes = ; #interrupt-cells = ; interrupts = ; interrupt-names = "msi"; clocks = ; clock-names = "pcie\0pcie_bus\0pcie_phy\0pcie_per\0pcie_inbound_axi"; interrupt-map-mask = ; interrupt-map = ; power-domains = ; fsl,max-link-speed = ; hsio-cfg = ; hsio = ; ctrl-id = ; cpu-base-addr = ; status = "okay"; ext_osc = ; pinctrl-names = "default"; pinctrl-0 = ; reset-gpio = ; clkreq-gpio = ; };

pcie@0x5f010000 { compatible = "fsl,imx8qm-pcie\0snps,dw-pcie"; reg = ; reg-names = "dbi\0config"; reserved-region = ; #address-cells = ; #size-cells = ; device_type = "pci"; ranges = ; num-lanes = ; #interrupt-cells = ; interrupts = ; interrupt-names = "msi"; clocks = ; clock-names = "pcie\0pcie_bus\0pcie_phy\0pcie_per\0pcie_inbound_axi"; interrupt-map-mask = ; interrupt-map = ; power-domains = ; fsl,max-link-speed = ; hsio-cfg = ; hsio = ; ctrl-id = ; cpu-base-addr = ; status = "disabled"; ext_osc = ; pinctrl-names = "default"; pinctrl-0 = ; clkreq-gpio = ; };

pcieagrp { fsl,pins = ; linux,phandle = ; phandle = ; };

pciebgrp { fsl,pins = ; linux,phandle = ; phandle = ; };

So it is clear, that the PCIe controller at 0x5f000000 is connected to port A, while the PCIe controller at 0x5f010000 is connected to port B.

Therefore, I have moved the XTRX module to the M2 PCIe port (using the adapter that was delivered together with XTRX), switched off the controller at 0x5f000000, and switched on the controller at 0x5f01000. Changing the active controller was done in U-Boot:

run loadfdt; fdt adr $fdt_addr ; fdt resize fdt set /pcie@0x5f000000 status disabled fdt set /pcie@0x5f010000 status okay run mmcargs; run loadimage ; run boot_os

After the above, the system booted correctly, and I could see the below messages.

In the boot log: [ 1.131045] imx6q-pcie 5f010000.pcie: 5f010000.pcie supply epdev_on not found, using dummy regulator [ 1.140117] OF: PCI: host bridge /pcie@0x5f010000 ranges: [ 1.145238] OF: PCI: No bus range found for /pcie@0x5f010000, using [bus 00-ff] [ 1.152716] OF: PCI: IO 0x7ff80000..0x7ff8ffff -> 0x00000000 [ 1.158615] OF: PCI: MEM 0x70000000..0x7fefffff -> 0x70000000 [ 1.165678] imx6q-pcie 5f010000.pcie: pcie phy pll is locked. [ 1.186275] imx6q-pcie 5f010000.pcie: Link up, Gen2 [ 1.191791] imx6q-pcie 5f010000.pcie: PCI host bridge to bus 0000:00 [ 1.197815] pci_bus 0000:00: root bus resource [bus 00-ff] [ 1.203277] pci_bus 0000:00: root bus resource [io 0x0000-0xffff] [ 1.209444] pci_bus 0000:00: root bus resource [mem 0x70000000-0x7fefffff] [ 1.226960] pci 0000:00:00.0: BAR 0: assigned [mem 0x70000000-0x70ffffff 64bit] [ 1.233945] pci 0000:00:00.0: BAR 6: assigned [mem 0x71000000-0x71ffffff pref] [ 1.241151] pci 0000:00:00.0: BAR 14: assigned [mem 0x72000000-0x720fffff] [ 1.248019] pci 0000:01:00.0: BAR 1: assigned [mem 0x72000000-0x7200ffff] [ 1.254797] pci 0000:01:00.0: BAR 0: assigned [mem 0x72010000-0x72010fff] [ 1.261581] pci 0000:00:00.0: PCI bridge to [bus 01-ff] [ 1.266773] pci 0000:00:00.0: bridge window [mem 0x72000000-0x720fffff] [ 1.274430] pcieport 0000:00:00.0: Signaling PME with IRQ 413 [ 1.279946] pcieport 0000:00:00.0: AER enabled with IRQ 414

And as the output of the lspci:

root@imx8qm-cgtsmx8:~# lspci -v -v