Hi
That's about 20MIPS on an 8 bit data bus with 17 bit addressing, no on chip cache.
Cheers Jacko
just put up nibzWW.vhd, a major bug fix edition. still planning some nibzX features, but have built some in, found some missing not gate typpo things and in general improved some routing and timing aspects. slight change in the DMA read bus to reduce multiplex input combine to specific registers.
cheers jacko
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