In fairness, the verilog2001 support is not the issue. The main reason the source did not compile was XST's adherence to some rules, like naming generate statement begin blocks, etc, and an issue with using clogb2 in a parameter. All small issues really - few tweaks here and there, took me a half an hour to do, and it synthesized!
This was for a (very) basic configuration, I just tried to synth this to the slowest speed grade V5,
Number of Slice Registers: 780 Number of Slice LUTs: 1174 Number used as Logic: 1046 Number used as Memory: 128 Number used as RAM: 128
and it came out at 170MHz (post synth timing only - did not run PAR). Would be Interesting to see if it works, and with more features turned on..though I have no time to test it.. But XST can do it - with relatively small amount of code massaging.