Hi,
I'm trying to squeeze every last mW out of some deeply embedded designs. To do so, I'm opting to power down "external" peripherals/support kit when not required. But, so far, it's been pretty much an ad hoc process; tweeking each design as best I can and tallying up individual savings on a "per design" basis.
I'd much prefer a more systematic approach -- even if it adds to my BoM.
Ideally, I'd like to operate:
- completely dormant (wait for external event to bring things back up)
- minimal capability (processor running with very few I/O's -- possibly internal and/or external)
- reduced capability (processor running with most I/O's except some particularly power hungry sorts)
- full capability (everything spinning)
By way of example, for an IP camera;
- completely dormant (nothing happening; keep *fleas* warm!)
- minimal capability (processor and NIC running; waiting to be commanded "on")
- reduced capability (processor, internal I/O's, external RAM running but camera, Ir illuminator, PTZ off)
- full capability (processor, internal I/O's, external RAM, camera, Ir illuminator, PTZ mechanism on)
From this, you should be able to envision subsets that are useful without consuming maximum required power (e.g., Ir illuminator off during daylight hours).
For this example, some subsystems are relatively easy to power down -- e.g., remove power to the PTZ mechanism and there are just a few control signals involved. But, others require more finesses (e.g., powering down external DDR).
Anyone been down this path, before, that can offer useful insights? My current issues are hardware related (interface constraints) but there are obvious software repercussions, as well.
Thanks!
--don