So, I'm trying to attach some DDR SDRAM to a blackfin DSP. It's the first t ime I've tried to lay out DDR, and I'm not finding it easy-going...
Here's an image of the left side of the DSP and the entire DDR chip... http ://0x0000ff.com/imgs/eagle/bga-ddr.png.
In line with what I've been reading, I was trying to get CK,/CK laid out fi rst, then sync up address[0:15], ba[0:3], /RAS, /CAS, /WE, and /CKE. Even a t this first stage, it's looking like it's going to be hard - the different ial clock signals need to be (a) parallel to each other and (b) the same le ngth (or near as makes no difference), and then all the others above need t o match to within 100 mils of the length of CK!
This doesn't begin to compare to the full list of restrictions (all traces under 1.1", bytes lanes length-matched, traces in same group on same layer, all traces to be one layer away from a full ground plane,... the list goes on).
I'm using Eagle, have done for years, and its not really helping me at this point. Trying to route the differential pair CK, /CK as an actual differen tial pair makes it ignore the design constraints that have been set up and even routes the paired signal over another pad while you're routing the fir st of the pair.
So, is there anything out there that is (a) relatively cheap (this is still a hobby, and I've a $3k BGA placement machine already budgeted for, I don' t want to spend *too* much more...), and (b) does a good job ? Eagle's been great up until now, but I can't help but think I'm pushing its limits. Or am I wrong in this, and do all PCB layout engines suck, and this task (DDR routing) is just way harder than it ought to be ?
Cheers Simon