Hello!
Can anyone help me validate (true/false) the following statements:
"Using the to put video information into a digital system, I don't need to take care of any of the vertical and/or horizontal synchronization pulses, as they are embedded in the data stream"
"Using the 8-bit parallel version of the ITU-R BT 656, I only need 9 inputs (including clock @ 27 MHz) from my FPGA to get the video stream into the device."
Thanks!
Fran.
Sorry for the mistake:
ITU-R_BT_65
True: Syncs are embedded and have values 0 and 255. True: 656 Parallel data uses a bus of 9 pairs balanced ECL at 100 ohms. I guess you'll need line drivers for this.
Peter
Mowcowmoo is correct but I would go on to say that in the modern world most studio 656 interconnect is done in 10 bits rather than 8 as a modulated bit serial stream on coax at 270 Mb/s. This is usually called SDI.
You should really find out what you are trying to interface to with the 656 stream before you commit to the older 8-bit parallel interface.
I am actually getting the video input from a PAL decoder (Philips SAA7111A) and putting it back to a similar encoder to see the video out. So, I don't use the stadard for transimission purposes, but only interfacing.
Thanx to both of you.
YES
YES
... one small warning , if you intend to generate the 27mhz on the fpga, send it to the decoder, have the decoder output 27mhz clk clock the data into the fpga ... be warned that depending upon the decoder and video the decoder output clock can be quite jittery and cause problems .. you may want to consider implementing a small fifo on the input video data to have a solid output ...
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