I am writing an VHDL test bench model to generate BT.656 digital video data for NTSC and PAL. so , out put of that test bench is digital data comprising SAV, BLANKING, EAV and ACTIVE VIDEO. I want to test this digital data is correct or not. AS this VHDL model is a test model which uses loops etc. and so not synthesizable. so I can not dumo it into FPGA. Can anybody suggest me the way to test this test bench model to verify the output digital data is correct data or not