(CY7C68013)
low
tested
HS OTG
Antti -
Approximately how many FPGA gates would the USB 3300 IP core solution consume? Also, when this IP core is inserted and compiled for the FPGA what clock speeds will be required in order to reduce the possibility of internal timing problems?
We have an FPGA available that will be used for several other functions but it's currently unclear how many gates will be available for this IP core or any other additional functions.
Brad S.
Brad,
If you don't need OTG but just HS host, you can use also ISP1760. You can download datasheet here:
The part is marked "Full production", but I don't know if it's true or not. Tomorrow I'll give them a call.
Antonio,
Thanks for the link. I downloaded the datasheet and it looks like we could use it but we only need one USB 2.0 port and this part has three (3) ports so it would definitely be overkill. Also, understandably, the part is large (128 pins) and we are trying to conserve as much power and PCB space as we call.
If I remember right, I believe the ISP1761 only has one port but isn't available to the general public yet. I'll keep looking. Thanks for your help.
Brad.
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