I was having a small problem interfacing a linux driver with a PCI card (FPGA with OC PCI bridge Core). I was having problems when sending data to addresses different from multiples of 4 (e.g 1, 2, 3,
5...)..After some homework i think i could find the explanation to my problem. Reading the PCI spec, i could see that on memory space transactions (read and write), the bits 0 and 1 of the AD line on the addressing phase are not part of the address, so i belive they are aways considered as 0. So when i send something on the address 1, it is going to perform 2 transactions, one with byte 0 1 and 2 of my data related to the address 0, and a second one with the byte 3 related to the addres 4. Am i assuming that correct? Is that how linux drive the PCI bus when you send data one address 1 (or 2 .. 3 .. 5 and so on)? I could find on many places that x86 cannot perform burst transactions, but when i write to an address 1 i see just one transaction on my PCI side (i am monitoring when my device sets TRDY) and 2 on my Wishbone (it does not suport burst yet), representing that 2 DWORDs were received. But when i read address 1 (always relared to BAR1) i see 2 transactions on the PCI bus, and 2 on the wishbone bus. So x86 can burst write but not read? And more weird, most addresses behave like that but 5, 6 and 7 generate 2 write transactions (i did not test all the others addresses, just some of them).. any idea why?Thank you for the help!