ATTiny26 TWI slave operation

In SetTWISlave:

That should be 0xF0, or in Atmel-ese: (1

Hi Gary,

Thanks for replying.

Ah, yes. That mistake too. I'm making silly mistakes now. But it still doesn't work. I've also tried setting USIWM1=1 and 0

As far as I can tell, you are doing things right and should get a TWINT at NOTE1. You do have some sbr instructions that I assume are skipping around some of the debug code you left out. I'm wondering if your debug code is messing you up.

As far as I can see, the TWI Module shouldn't even care if anything is out there. If you put something in the data register and clear the TWINT flag (with TWEN set), it should shift out the bits and then set TWINT. So, something very strange is happening.

Yes, The registers iTmp2 and iTmp3 in the master are just for debug. I'll try removing all the debug code just for fun and see what happens.

Perhaps I just need some sleep. :) I have never had something that seems so simple cause me so much grief. I can't help feeling there is some minor thing I am missing.

Thanks for looking at it.

Regards

- Mike

I am missing.

I know that feeling! I think many of us here have had that. I have found it's never good to code when you are sleepy. I can't tell you how many times after a good sleep that the solution comes to me.

I've done some of my best debugging during my morning shower. And no, I don't take a listing in with me...

Regards,

-=Dave

This is just a random thing - I don't use I2C... er... I mean 2-wire interface. But, do you have handlers for all interrupts? On AVR I vector all unused interrupts to a routine that sets an "invalid IRQ detected" flag and either halts or sets a bit that communicates the spurious interrupt condition back to the master.

I've solved the problem.

It was what I believe to be a mislead "The Serial Data (SDA) and the Serial Clock (SCL) pins are bidirectional and uses open-collector output drives. The output drivers are enabled by the DDRB0/2 bit in the DDRB Register."

and...

"When the SCL pin output driver is enabled the SCL line will be forced low if the PORTB2 bit in the PORTB Register is zero, or by the start detector. Otherwise the SCL line will not be driven."

and...

"The SCL line is held low when a start detector detects a start condition and the output is enabled."

In my slave set-up I was doing:

sbi PORTB,SCL sbi DDRB,SCL

Does that not enable the SCL line?

Anyway, the SCL line in not held low when start is detected. This caused the bit counter to end up overflowing half a clock pulse too soon.

To cure it, I now wait in the start detect routine for SCL to go low, then set the counter. It seems to work so far.

Now, maybe I can move on to making it actually do something. :)

-Mike

Yes. I always create handlers for all the interrupts. It's in my template for new projects.

Anyway, I seem to have solved it. See my latest reply to Gary.

-Mike