Ethernet MDI termination

The paired MDI signals from the PHY to the magnetics in a GbE application are each terminated by a 50R resistor and then together to a 10nF capacitor to GND. However some applications connect the 2 resistors to Vcc (2.5V) as well. Can anyone explain why some configurations are like this and others aren't? Is it something specific to the magnetics?

TIA,

Rog.

Reply to
Roger
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It's not clear from your post whether you are talking about the same PHY used differently or different PHYs. PHY output drivers can be either voltage or current mode. Current mode drivers require pullup to a voltage source. Some PHYs have different dirvers in different modes of operation (e.g.

10BaseT vs. 100 or 1000BaseT). Also, there are a few different types of magnetics used, which might require different termination schemes. Try to find appnotes relevant to the PHY you are using.

/Mikhail

Reply to
MM

Thanks for the reply. I've tried very hard to find something definite regarding the PHY I'm using (Marvell 88E1112) but can't. In my original post I meant different PHYs seem to be connected differently. From what you say, IF the 88E1112 is a current mode driver, connecting to 2.5V could be the correct thing to do.

Roger.

Reply to
Roger

Companies making Ethernet PHYs are very secretive for whatever reason. You need to talk to them to get access to even the most basic information. An NDA might be required, which is difficult to arrange if you don't work for a business. However, if you manage to get access, you will find that there is a lot of information available. A while ago I chose a different vendor because Marvell was slower to respond to my requests for nformation.

/Mikhail

Reply to
MM

Thanks for your reply. I have an NDA with Marvell and there is a fair bit of information to be had but I still can't find the answer. I've asked for help from them but they're not very responsive! I don't know why they're so secretive.

Rog.

Reply to
Roger

Since you are posting on c.a.f. you are probably following one of the FPGA eval board reference designs, right? Xilinx ML403 board uses a Marvell chip. I don't remember the exact P/N, but it is something similar to yours. Newer V5 boards might be using newer chips... If you follow one of these examples you should be pretty safe even if you don't understand all the details of the circuit...

Also, why don't you post a link to the circuit in question and someone might be able to give you a better advice....

/Mikhail

Reply to
MM

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