mentions that the Ethernet standard is "IEEE 802.3ae-2002". That's the 10Gbps standard! I suggest you change this to "IEEE 802.3-2002 -- Section One". Here is the direct URL:
formatting link
Chapter 14 (10Base-T) is the relevant part of that document.
There is no way your circuit will meet many of the Ethernet electrical requirements (section 14.3 in the spec). Whilst it may pass data, and be of great educational value, I think you really should have a statement on your website saying that this isn't Ethernet compliant, otherwise newbies will think that it really is Ethernet and start designing it into their own products.
You probably do need the transformers, otherwise the section
14.3.1.1 isolation requirements of 2400V (yes, that's 2.4 kV) are a little difficult to meet. The 1kV common mode surge requirments in 14.3.1.2.7 (transmit) and
14.3.1.3.6 (receive) may also be difficult to meet without a transformer.
The receiver may work better with a 120ohm (or so) resistor between the RD- and RD+ pins. This should give the receiver a better return loss (which is meant to be 15dB minimum, according to
14.3.1.3.4), and might improve the performance on long cables.
BTW, what error rate did you get over 100m of cable?
Whoa, good, that's what I needed, a guy who knows a little more than I do about the Analog Ethernet requirements. I'll make the necessary updates on the site.
I didn't try long cables, that probably explains it why I didn't run into problems. Will do, and try with 120ohms resistors. Thanks. Jean
Allan, did you get my email yesterday? I sent you a few screenshots.
Anyway:
is fixed.
and 3. Looks like the way to meet the spec is to buy an isolation transformer and follow the apps notes, a good source seems to be
formatting link
so it should be just a matter to buy these.
4., I did more experiments with a longer (30m) cable, and the results are surprisingly good. Reflection from a terminated cable (connected to an Ethernet switch) are low, even when driving directly from the FPGA. Putting
50ohms or 100ohms series resistors doesn't have much influence besides attenuating the incident signal. In all cases, I did not seem to experience any packet drops.
Also try Prem, Pico, Midcom, Halo, Gowanda, etc. Note that these transformers will be designed to work with different PHYs, and each PHY will require a different turns ratio (which determines the impedance ratio, and is sometimes not 1:1) and can tolerate a different amount of leakage inductance. This means that pulling a transformer out of any old 10Base-T Ethernet card isn't guaranteed to give good results with your design. (Of course, you can get the part number of the PHY from the Ethernet card and look up its specs to find out what the transformer is like.)
If your design already works with a direct connection to the cable, I suggest starting with a 1:1 transformer.
Ummm, those reflections are a function of the terminating impedance (i.e. the Ethernet switch), so you'd expect them to be low. The comment in my earlier post about terminating impedance was to do with the input of your circuit, which affects the reflections of the signal coming from the other end. A resistor across RD-/RD+ should make this better.
Yes, there are lots of manufacturers of magnetics.
I found this page
formatting link
About the reflection, since this particular experiment is an emitter only, I'm relying on the other end device (an Ethernet switch) to do proper termination (which it does, according to my measurements).
Once I work further on the receiver part, I certainly need to pay attention to terminating the lines i.e. putting a resistor across the pair. Thanks. Jean
It is still best to terminate both directions, but it will generally work if you terminate one end, for protocols that only send one direction on each pair.
As you say, if the receiver is terminated, there won't be a reflection. It the transmitter is properly terminated, the reflection from the receiver will be absorbed at that point, and won't cause problems (most of the time).
When you get to gigabit, using both directions on each pair at the same time, proper termination of both ends is much more important.
Termination at both ends for unidirectional systems allows a tolerance for mismatch. If 10baseT is terminated at 120 ohms, then using cable between 100 ohms and 150 ohms will result in at most about 20% reflection. At most about 20% of that, or 4% of the original will then reflect back again from the other end.
That makes sense. Terminating the receiver is just a matter of putting a resistor across the wire pair.
Now, the question is, how to terminate the transmitter?
If I assume cat5 cables (100ohms differential impedance?), my first thought is to put two 50ohms series resistors on the transmitter side. The downside is, it is going to cut in half the incident wave. Any better way? Jean
14.3.1.2.2 indicates that the return loss has to be at least 15dB (between 5.0MHz and 10MHz).
Most approaches for driving terminated lines with good output return loss will lose half the output power in the driver. There's not too much you can do about this if using an FPGA.
You don't say whether the FPGA I/O is powered from 2.5V or 3.3V. This makes a difference.
For best output return loss, (R1 + R2) * N^2 = 100 ohm. (You should include the output resistance of the FPGA drivers in R1 and R2 - see the IBIS models.)
The (single sided, not peak to peak) output amplitude will be
Vcc * (100ohm / (100 ohm + (R1 + R2)/N))
E.g. Vcc = 3.3.V, N = 1 (i.e. it's a 1:1 transformer, a very common type) then to get the right output amplitude, R1 and R2 will need to be at most 25 ohms each (including the FPGA output resistance). This gives an output impedance of 50 ohms though, which is equivalent to a return loss of only about 9.5dB.
Hmmm. The only thing to do (apart from violating the specs) is to use a stepup transformer. This is actually what most PHYs do (more or less).
A 1:2 transformer would work well with a Vcc of 2.5V. R1 and R2 would still be 25ohm, but the output amplitude would be 2.5V, with a good return loss. However, the current in the FPGA output pins would be 50mA. This probably isn't practical without using multiple drivers in parallel.
A 1:1.3 transformer would work well with a Vcc of 3.3V. R1 and R2 would need to be about 30 ohm, and the FPGA output current would come down to about 32mA.
Note that 14.3.1.2.1 says "[the] transmitter shall provide equalization such that the output waveform shall fall within the template shown in Figure 14?9 for all data sequences" as well as "any harmonic measured on the TD circuit shall be at least 27 dB below the fundamental." There is no simple way of providing equalisation when using such a simple driver.
Thanks for the *detailed* answer. I used 3.3V IOs, so I need an 1:1.3 transformer to meet both amplitude and return loss. I guess that if I want to use common 1:1 transformers, I need 5V IOs and
50ohms resistors.
For the equalization and harmonic requirements, couldn't I use a filter?
27dB is pretty sharp though, doesn't seem easy. Looking at some PHY/transformer schematics doesn't show any filter. Is it usually provided inside the PHY?
Yes, that would also give a good output level and return loss. The FPGA pin current would be 25mA, which would probably be possible without needing to double-up output drivers.
There is a direct tradeoff between current and voltage at the FPGA pins which is determined by the transformer ratio.
(ASIC) PHYs often drive into a centre tapped transformer. The centre tap is connected to VCC (or sometimes GND). The outputs only pull down (one at a time), and the transformer action makes the voltage at the other output rise above the supply rail. This allows more voltage swing from a given supply voltage, but can't be done in an FPGA due to restrictions in the voltages that can be applied to output pins. (Or can it? You might get lucky with some 5V compliant parts running from lower voltages.)
It's not easy. You'd also need a buffer amp after the filter, otherwise the line impedance will affect the filter response and it will also be difficult to get a good (wideband) return loss.
The (FIR) filter is implemented digitally inside the PHY. You can also think of this as "pulse shaping" rather than filtering.
This sort of thing just isn't feasible inside an FPGA, unless you use some sort of DAC on the output. ("Some sort of DAC" could be as simple as a small number of resistors though.)
This sci.electronics.design thread:
formatting link
discusses the design of a pulse shaping filter for an ASIC. The designer ended up with a combination of an FIR filter (implemented with a weighted resistor network) inside the ASIC and a single pole LP filter outside the ASIC to achieve the required pulse shape (and hence frequency response).
ok, so the PHY has some analog job to do. If I make some experiments, I'll look for a solution with a low pin count. Maybe an R-L filter. It might be interesting to put all this info available on my site, even if that's more analog than digital.
In any case, thanks for all this info, I didn't suspect there was so much analog work involved. Jean
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here.
All logos and trade names are the property of their respective owners.