Bootstrapping to eliminate parasitic capacitances

Here's a step by step look at the subject

ASCII art:

First step: an ideal Gain=1 In ---+------!>-------+---- Out ! ! [Z1] ! ! ! ---------------

Assume that Z1 is anything other than zero. Since the Z1 has exactly the same voltage on each end, there is no current in the Z1. With no current in Z1, the impedance looks infinite.

Gain=1 In ---+------!>-------+---- Out ! ! [Z1] ! ! ! +------[Z2]----- ! [Z3] ! gnd

If at some frequency, Z2 is very small compared to both Z1 and Z3, at that frequency, the current in Z1 is small. At that frequency the impedance will be very high. Z1 and Z3 could be a couple of resistors and Z2 a capacitor for example.

Now lets make the ideal gain into a MOSFET:

d !!-- Vcc In ---+------!! ! !!-------+---- Out [Z1] s ! ! ! +------[Z2]-----+ ! ! [Z3] [R1] ! ! Vbias Gnd

We've had to add a Vbias to the end of Z3 and dd the R1 as a current path of the source current. Again, it is most likely that Z2 will be a capacitor. Z1 and Z3 will have gotten more complicated now because the MOSFET has capacitances.

Note: The Z1, Z2, Z3 circuit still only needs to have 3 parts in it because by a bit of math you can turn the MOSFETs Cgs and Cgd into a change in the 3 values. When you do, you will find that Cgs doesn't have, propotionally as much effect as Cgd.

Now lets boot strap the Cgd

d !!-- Vcc Out --[Z4]---+------!! Q2 ! !!-- [Z5] ! ! ! VBias2 ! ! d ! !!-------- In ---+------!! Q1 ! !!-------+---- Out [Z1] s ! ! ! +------[Z2]-----+ ! ! [Z3] [R1] ! ! Vbias Gnd

Notice how we have added a second device that is getting its signal from the circuit output. Z4 is likely a capacitor and Z5 a resistor. Q2 ensures that all three of the terminals of Q1 all move together. If the gains are high the input impedance can be quite high.

Great message Ken, thank you. Let me add a few comments:

Can Cgd really be absorbed into Z1, Z2, or Z3? Since it's effectively going from the gate to ground.

Very nice. Could you simplify this a little (at still get most of the performance improvement) by just running Q1's drain to an appropriate bias voltage and then just placing a capacitor across Q1's drain and source? I'll try this in SPICE...

---Joel

Look up Y to delta converting. You will find that Cgd appears as a decrease in Z1 and Z3 and a increase in Z2.

No, this will never work. Don't use SPICE. Think. Think about what the transistor does when it turns on and off. Think about making the capacitor in your suggestion have zero impedance. At some point you will say "aha!" and enlightenment will begin.

Hi Ken,

Will do.

Ah... it shorts out the current gain of the 'FET, so that's probably not so cool. :-)

So the deal is that -- from a small signal point of view -- when the drain of Q1 "looks" back into the source of Q2 it "sees" a (nearly zero impedance) source voltage, rather than seeing its own drain... interesting...

In article , Joel Kolstad wrote: [...]

It depends on how the Q1 does its looking. Notice that Q2 conspires to force the drain voltage to have the same waveform as the source.

BTW: I've done impedances over 200G in parallel with 0.2pF. You could see someone combing their hair at over 10 feet away. All testing had to be done using a shield room with a port in the side.