Hi everybody,
I'm in a research phase to develop an ieee1394 device and I'm studying the standard specifications plus TSB12LV32 datasheet, but I've some doubt and unfortunately few informations are available, I hope someone of you used this chip and can help me. For the device I have in my mind data mover port will be connected to a FPGA that will feed high data rate to transmit in isochronous way, while a microcontroller send/receive asychronous data for device registers/configuration via FIFO. What I don't understand is: after I fill FIFO with quadlets relative to more than one transactions, if FIFOACK goes to active state when ack is received for a packet sent via FIFO, how can I know which was the last packet ? I immagine that TSB12LV32 will continue to try to transmit packets at very high speed and in the time microcontroller handles the interrupt condition all FIFO can be flushed ! I'm asking this because to implement transaction layer I need to know when ack is received for a particular packet.
Thank you in advance to everybody. Best Regards, Simone Navari.