I am using a ADSP blackfin Bf533 processor, i have only sport Rcv and Sport Tx Dma configured for ethernet rcv and tx respectively. I run a loopback code to loop packets from sport Rcv to Sport TX (with an intermediate SDRAM copy). Sport Tx dma often stalls and leads to a dma stuck up condition.
things i have observed:
----------------------------- (i) DMA stuck up does not occur if intermediate copy is in L1 instead of sdram (ii) If core is kept busy for the duration when Sport Tx Dma is running by using some delay loop (i.e. core does not access anything else.. just waits in a loop till sport Tx dma is complete), then the dma never stalls (even if the intermediate buffer is in SDRAM)
---------- (i) Does BF533 have a problem with DMA (from L1) and SdRAm access running parallely. ( I tested this in another test code, but found no problems..) (ii) If not, then what else could be the reason for the sport tx Dma stalling.