Amtel SAM9 "boot from NAND" is a myth?

Cripes. Hopefully, Ulf will take a moment to provide a frank and complete response to your experiences here.

Jon

Product Marketing: "We need to boot from NAND flash"

Engineering: "We're six months away from tape out, you can't add a new feature now"

Product Marketing: "Men women and children will die if you don't make this work"

Engineering: "Well, get the executive cadre to move tape out by nine months and we'll do the job right"

Product Marketing: "We can't do that. Just make it work or you're all fired".

Engineering: "OK..."

Which Dilbert book is this from? Only trouble is, marketing can't fire anyone in engineering... as much as they might like to.

This sort of program uses all manner of concept, requirement and specification documents. But that is no replacement for thinking. This is just something that no one thought about at the time.

Maybe I"m showing my ignorance, but I thought the ECC was ON the flash part and was hidden from the MCU. Is that being turned off or did I miss something in how NAND flash works?

Rick

The last time I looked at NAND flash the ECC part was just extra bits in each record -- it was your job to fill them in on writes and interpret them on reads.

Of course, that was 5-10 years ago.

Then somebody screwed up, becuase it was their job to think about that sort of thing.

Not in any of the NAND flash datasheets I've seen.

Yup. And the NAND controller in the SAM9 part _has_ hardware that generates the ECC bits when you do a write operation. All you hvae to do is write them into the "extra" bits in the flash after you've written the data. Reading is a bit more complex, since there's extra work required to correct an error when one is detected.

It's still that way. There may be NAND parts that do ECC themselves, but I've never seen one.

For what it's worth, Micron MT29FxGxx has a guaranteed good block 0.

This is not unprecedented. In fact the original SSFDC specification, I believe, had the same requirement (it has been a VERY long time, but IIRC the first block had to contain the CIS, and it had to be 100% free of errors, both correctable and uncorrectable).

We're shipping a product based on a micro with the same limitation. I believe bad block 0s are treated as a normal production yield issue (the parts are programmed in-circuit).

I also think the i.MXxxxxxxxx family from Freescale has the same requirement. Anyway it's definitely not the first time I've heard it mentioned.

Never attribute to malice that which can adequately be explained by stupidity. And I doubt DataFlash is a major revenue generator for Atmel.

The idea of NAND is cheap bulk storage, no on-chip smarts, move the cost into the main micro.

At least Samsung's S3C2440A has the same requirement.

-a

At some point in the past, perhaps it was thought that bit-error-free block 0 was going to be a common spec for NAND flash parts?

Apparently nobody told the guys running the flash fabs...

I have found a datasheet for one 1.8V NAND flash that guarantees a good block zero. Whether the parts are actually available or not I don't know.

Unfortunately we want to run the flash at 3.3V, and the distributors/FAEs we've talked to have been unable to _any_ 3.3V part thats meets Atmel's defect-free block 0 requirement. Now the choice is between adding a SPI flash for booting or adding 1.8V rail plus buying more expensive 1.8V SDRAM along with bus transceivers to talk to the required 3.3V peripherals.

But don't all manufactures guarantee this?

When I worked on NAND that as the spec -

Block 0 was guaranteed to work (so that you could boot from it) and all the rest could be replaced by error checking.

devices with errors in block 0 are scrap.

tim

Nope.

For example, from Micron's datasheet for the MT29F1G08/MT29F1G16:

• Blocks 0\u20137 (block address 00h-07h) guaranteed to be valid with ECC when shipped from factory (3.3V only); see Error Management (page 83).
• Blocks 0\u20133 (block address 00h-03h) guaranteed to be valid with ECC when shipped from factory (1.8V only); see Error Management (page 83).

From p83:

The first block (physical block address 00h) for each CE# is guaranteed to be valid with ECC when shipped from the factory. Blocks 0-7 (block address 00h-40h) guaranteed to be valid with ECC when shipped from factory (3.3V only). Blocks 0-3 (block address 00h-40h) guaranteed to be valid with ECC when shipped from factory (1.8V only).

That doesn't currently seem to be the case.

Makes sense to me.

Not any more.

From what the local Arrow guys have told us, it seems most newer parts don't guarantee block 0 good unless you're doing ECC that can correct a single-bit error.

Coincidentally Samsung's own K9F1208 is a 3.3V part and guarantees an error-free block zero. It's not advertised as a feature, but reading the datasheet you find this:

"The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase cycles."

I don't have enough experience with NAND flash to say if this is a common feature or not. (I'm only aware of the S3C2440 and this flash via the FriendlyARM Mini2440 board.)

-a

All "hardware ECC support" I have seen so far is useless for anything but older, smaller SLC parts. "Hardware ECC support" is doing a Hamming code in hardware, which can correct a single bit error. Current large SLC parts, and MLC parts, need a 4- or even 8-bit-correcting code.

Thus, "NAND flash support" is another piece for glossy brochures. A regular memory interface and an interrupt-capable GPIO is enough to access NAND flash.

I haven't seen anything but announcements (or fully-fledged SSDs / memory cards).

Stefan

See what they (Hynix, Intel, Micron, Phison, SanDisk, Sony, Spansion) have spec'ed about NAND at

From the Hynix HY27USXX561A data sheet: - 3.3V device: VCC = 2.7 to 3.6V : - The 1st block is guaranteed to be a valid block up to 1K cycles without ECC

Can you please point to that in the spec?

All I can find is the definition for one of the fields in the parameter block that tells how many valid blocks there are at the beginning of the device:

Version 2.0:

Guaranteed valid blocks at beginning of target This field indicates the number of guaranteed valid blocks starting at block address 0 of the target. The minimum value for this field is 1h. The blocks are guaranteed to be valid for the endurance specified for this area (see section 5.6.1.21) when the host follows the specified number of bits to correct.

Versions 2.1,2.2,2.3:

Guaranteed valid blocks at beginning of target This field indicates the number of guaranteed valid blocks starting at block address 0 of the target. The minimum value for this field is 1h. The blocks are guaranteed to be valid for the endurance specified for this area (see section 5.6.1.23) when the host follows the specified number of bits to correct.

Nowhere does it say this number can't be 0, and it explicitly says they can require that the host do ECC for those "garanteed valid" blocks.

Yup, I just found that one about 10 minutes ago. Unfortunately, Hynix has no local distributors and we're not large enough that Hynix sell to us, and we've been burned recently buying gray-market flash.

I've also just found a couple Micron datasheets that spec block 0 to be valid without ECC, but apparently those parts aren't available according to the local Micron rep.

Ah. That appears to be a lower-desnity small-block part (512Mb). I'm not sure what size we told the rep, but it looks like it was 1Gb or based on the datasheets I've seen so far. We're also only interested in parts we can actually buy, so it's also possible the K9F1208 isn't avaialable through distribution.

Duh, wrong. The minimum is 1.

I still stand by that reading.

They have other parts, like the K9F8G08 (1GB, 4K pages). Dunno about availability.

-a