about MIPS Kseg0 access issue

As we know in mips achitecture if current pc falls into kseg1 segment, any memory reference will bypass cache and fetch directly from dram. But for some prcoessor such like mips R10K it has off chip L2 cache. I haven't found any available path where can access dram directly. all memory reference need go through L2 cache. Does it means any memory reference in kseg1 will be fetch from L2 cache nor dram for such system? How to initiate L2 cache when system bootstrap?

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