MIPS 4Kc Cache Initialization

Howdy,

I'm working a MIPS 4Kc-type chip from Broadcom. I'm having trouble with the cache initialization function. My code is based entirely on the code from the book _See Mips Run_. When I change_cp0_config (0x7, 3) after the setupCache() call the board reboots. Similarly, linux crashes doing its own initialization. Any ideas?

void setupCache () { register unsigned int addr, junk;

write_32bit_cp0_register (CP0_TAGLO, 0); //I-Cahce: for (addr = KSEG0; addr < KSEG0 + 0x00002000; addr += 16) { Index_Store_Tag_I(addr); Fill_I(addr); Index_Store_Tag_I(addr); } //D-Cache: for (addr = KSEG0; addr < KSEG0 + 0x00001000; addr += 16) Index_Store_Tag_D(addr); for (addr = KSEG0; addr < KSEG0 + 0x00001000; addr += 16) junk = *((unsigned int *)addr); for (addr = KSEG0; addr < KSEG0 + 0x00001000; addr += 16) Index_Store_Tag_D(addr); }

One of the macros looks like so: #define Index_Store_Tag_I(i) \ __asm__ __volatile__( \ "cache 0x08,0(%0)\n\t" \ : : "r" (i) \ );

Thanks,

Brett