Which uController to learn?

plenty left

ARMs that

AIUI PICs are in the $1 range.

Embedded is embedded.

(now you sound like Dimbulb) I'm not a fscking programmer. I do it because it sometimes needs to be done.

--
  Keith

Or last at long as possible on battery.

I need uA in stand-by. Full speed (Usb or Serial) while connected. So, I need it very slow and very fast. For Serial, Avr tops at 19,000 baud and Arm tops at 920,000 baud. Avr has Usb option but Arm hasn't.

The phone line?

That would be a high duty cycle for a phone line, unless you need to wake up frequently to see if touch tones are being sent.

Yep, sounds right in line for a PIC though. 12F683 (my new favorite) ~500 uA at 5V running full tilt on the internal oscillator (8MHz, 1% accuracy),

11uA at 32KHz (2V). Change speeds on the fly. Who needs to sleep? ;-) You can sleep if you want, bit it'll cost you 50nA.

no it's not, it has too few registers to qualify.

It always seemed kind of awkward and slow slow to me.

Bye. Jasen

Many of them are doing 20 MIPS now, that wasn't available two years ago, built-in full speed USB is new too,

It's an 8-bit microcontroller it doesn't need that extra stuff ...

Bye. Jasen

that'd be because you're running such a slow clock. at only 1.8432 Mhz you can 115200 baud. basically 1/16 your clock.

yeah, but at what clock speed.

Bye. Jasen

No, it won't. At 2 MHz, AVR have lock-ups for 38,400 baud. My AVR clock toggles between 2 MHz and 32KHz.

20 MHz.

By whose definition? It stands for Reduced Instruction Set. 35 instructions is pretty reduced IMO.

Compared to what? 10MIPs on a few mA is pretty good in my book.

"lock ups?"

The attiny2313 "data sheet" suggests it should be capable of 250Kbps (asynchronous serial) at 2mhz

With a 2MHz clock 38400 baud isn't really an option on that hardware,

35714.3 or 41666.7 are the closest choices.

If you reduce the clock to 1.8432 Mhz (should be a standard size)

38400.0 is available (as are the other standard speeds upto 230400)

Not with the uart running I hope!

How does it manage that? 920K doesn't divide 20M, is there an internal PLL or something?

Anyway it seems kind of slow :^)

Some people bit-bang USB at 1.5Mb/s on 12Mz AVRs. (as a non-interruptable foreground task) again the trick is to pick a clock rate that's a sufficiently high multiple of the data rate.

Bye. Jasen

20 MIPS, on a MEGA. Those aren't backwards compatible with the tradition AVRs are they?

Speak for yourself. Since when is A/D resolution not important for an 8 bitter?

Actually, it stands for "Reduced Instruction Set Complexity". It has nothing to do with the number of instructions (PowerPC is certainly RISC, yet has hundreds of instructions in even more varieties), rather the complexity of the instructions. For example, no arithmetic operations on memory are allowed, only load/stores.

--
  Keith

RISC essentially means that EVERY instruction takes ONE clock cycle, so your clock speed is your IPS -- CISC chips like the 80x86 take anywhere from

4-??? instructions per clock, they internally decode instructions through a micro-code rom in the CPU that sequences the internal processing elements of the chip through the steps neccessary to perform the instruction -- for instance -- a single instruction may read memory, add it to a register, and write the result back to memory -- all in one instruction, but across multiple clock cycles.

Therefore there are things a CISC chip can do in one ASM instruction that a RISC chip cannot do, simply because there is no way to perform the operation in a single clock cycle... for instance -- the 80x86 has a single instruction memory copy capability for moving data around -- makes things a little easier on the compiler developers.

AVR32 based 32-bit MCU/DSP Vectored multiplier co-processor, 32 KB on-chip SRAM, 16 KB instruction and

16 KB data caches, MMU, DMA controller. Peripherals include a 16-bit stereo audio DAC, 2048x2048 pixel TFT/STN LCD controllers, 480 Mbps USB 2.0 with on chip transceivers (PHY) and, two 10/100 Ethernet MACs. Serial interfaces include RS232, USART, I2S, AC97, TWI/I2C, SPI, PS/2 and several synchronous serial modules (SSC) supporting most serial communication protocols.

sounds like a bit more than an 8-bitter to me !!

Nope. RISC == "Reduced Instruction Set Complexity". It has nothing to do with IPS. RISC is a philosophy. IPS is a design trade-off. The PowerPC *is* a RISC architecture. Some PowerPC implementations (e.g.. PPC750) tend to be one-cycle through the execution unit (plus decode, etc) where the Power5 is the same architecture and may be 5 to 15 cycles through the execution unit.

The x86 processors have memory reference arithmetec instructions (e.g.. ADD R,, thus CISC (the opposite of RISC). PowerPC has no like instruction.

It's RISC, not because it can do more than one thing per instruction, but because it can operate on memory with one instruction. BTW, RISC compilers are *far* easier to write; one of the reasons RISC was invented. RISC processors tend to be register rich, since they cannot operate on memory.

--
  Keith

This is an invalid generalization. Compiler complexity depends on many factors, and the raw size of the instruction set isn't even near the top of the list. Specialization is a more key factor, and RISC chips tend to have more specialized instructions. A CISC chip, for example, can usually add anything to anything, whereas RISC chips can only add registers, and sometimes add constants to a register.

The top of the list is usually "customer's requests for unique functionality".

Yes, an internal PLL at 200 MHz.

I have to slow it down to talk to the AVR anyway.

Unfortunately, they are often conflictings, i.e. USB vs. Serial.

I never said it was! Perhaps you'd like to read what I wrote. RISC small_instruction_set was one of my main points.

Nonsense. If anything RISC's instructions are less specialized. There aren't any string moves to memory, for instance.

That is pretty much the definition of RISC, so yes... They generally have LOTSA register though. It's easier scheduling data when you have lots of places to put it. Register management is more complex with CISC processors.

Huh? When does a customer request functionality from a compiler?

--
  Keith

When you write compilers for a living, as I do, and the customer is the one who created the chip you're targetting. They're usually the ones who pay for embedded development tools.

Slightly. ;-) Sounds allot like an ARM knockoff. I wonder what the power dissipation is on that, I'm guessing it's a bit more than my slow, cumbersome PIC. I bet it costs more than a $1 too. ;-)