What is power latch?

I'm supposing you are referring the tendency of the "A" series CMOS components (4000 series chips) to latch up when power is applied.

This is due to a parasitic SCR inherent in its design. Looking through the layers, there would be a PNPN structure. If this latches on, there would be a destructive current flow causing the chip to self destruct.

Sounds like the device attached to the back if the on/off button :)

Means they used google-translate or similar :)

Bye. Jasen

As ever Boki, you manage to have trouble describing your problem.

Now start at the beginning.......

Graham

==============

3.1 Startup 3.1.1 Startup Power Latch A shall enable the power latch upon startup.

3.1.2 Software Version Upon power-up, A shall write the software version to address 0x1234 ==============

:) Any advice?

Best regards, Boki.

If it is not clear from the document, then the document is incomplete. At a minimum, contact the individual who wrote the document; better yet, have him re-write it so that things are clear. Fuzzy specs benefit no one. . . This was my interpretation of the prose: Upon starting a Master Device, all slave devices are enabled. Example:

*-*-relay-via-a-current-transformer+When-I-turn-the-saw-on-I-want-the-dust-colector-to-automaticaly-come-on . . I sounds like Jasen interpreted the sequence of events correctly: (Google-translate).